3D BEOL MIM Capacitor Structure for High Capacitance
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Solution Overview
Problem
On-chip MIM capacitors face challenges in achieving large capacitance values without increasing chip area and causing signal interference, particularly when fabricated in the FEOL.
Innovation Solution
A 3D MIM structure is formed in the BEOL using a deep via hole through multiple dielectric layers, allowing for a larger surface area without additional fabrication steps, and utilizing a conductive etch stop structure to protect underlying metallization structures during etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a MIM capacitor is fabricated in a deep trench in the FEOL to achieve large capacitance values, then the capacitance value increases, but the chip area requirement increases and signal interference worsens
Solution Approach 1:
The patent transitions from planar capacitor geometry to a vertical 3D structure by forming deep via holes through multiple dielectric layers. This dimensional change allows the capacitor to achieve large capacitance values through increased surface area in the vertical direction rather than expanding horizontally, thus maintaining compact chip area while achieving high capacitance
Solution Approach 2:
The MIM capacitor structure is nested within the existing BEOL stack, utilizing the vertical space between metallization layers. The deep via hole penetrates through multiple dielectric layers and metallization structures, effectively nesting the capacitor within the established interconnect architecture without requiring additional lateral space
2Quantity of substance
If a deep trench MIM structure is used to achieve large capacitance values, then the capacitance value increases, but signal interference worsens
Solution Approach 1:
The patent extracts the capacitor structure from the FEOL region where active devices are fabricated and places it in the BEOL region. This separation removes the capacitor from the area where it would generate harmful electromagnetic interference with active devices, while still achieving large capacitance values through the vertical deep via hole structure
3Quantity of substance
If additional fabrication steps are introduced to form deep trench MIM capacitors, then capacitance values increase, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of the deep via hole with the existing via structure fabrication process in the BEOL. By integrating the capacitor formation into the standard interconnect fabrication sequence and utilizing the conductive etch stop structure that is already part of the process, the method achieves high capacitance values without introducing significant additional fabrication steps or complexity
Data Source
AI summary
Disclosed is a method of manufacturing a three dimensional (3D) metal-insulator-metal (MIM) capacitor in the back end of line, which can provide large and tunable capacitance values and meanwhile, does not interfere with the existing BEOL fabrication process. In one embodiment, a method for fabricating a semiconductor device includes: forming a first conductive feature on a semiconductor substrate; forming a second conductive feature on the semiconductor substrate; forming a first via structure over the first conductive feature; forming a first metallization structure over the first via structure, wherein the first metallization structure is conductively coupled to the first conductive feature through the first via structure; forming a conductive etch stop structure on the first metallization structure; forming a first via hole above the conductive etch stop structure and a second via hole above the second conductive feature, wherein the first via hole exposes the conductive etch stop structure and the second via hole is deeper than the first via hole; and forming a capacitor in the second via hole.