3D Bit Line Structure for Lower BL Plug Contact Resistance
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Solution Overview
Problem
The high contact resistance between bit lines (BLs) and BL plugs in semiconductor structures, resulting from a limited contact area and insulating material filling between adjacent BLs, hinders signal propagation speed and overall performance.
Innovation Solution
A semiconductor structure with BLs comprising a core layer and a conductive layer, where the BL plugs are in contact with the conductive layer, and vapor doping is used to reduce resistance, enhancing ohmic contact and increasing the contact area between the core and conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the capacitor is placed horizontally to reduce memory size and increase storage density, then the storage density is improved, but the contact resistance between the bit line and BL plug increases
Solution Approach 1:
The patent transitions from a conventional planar bit line structure to a three-dimensional stacked structure where bit lines are arranged in multiple layers (BL0, BL1, BL2, BL3) extending in different directions. This dimensional change allows the bit lines to connect to memory cells in a three-dimensional space, reducing the contact resistance while maintaining the horizontal capacitor placement for high storage density.
Solution Approach 2:
The patent implements a nested structure where multiple bit line layers are stacked vertically, with each layer containing bit lines that extend in different directions (e.g., BL0 and BL1 extend in a first direction, BL2 and BL3 extend in a second direction). The bit line plugs are nested within the stacked structure, connecting to different bit line layers at different heights, thereby reducing contact resistance through improved spatial arrangement.
2Ease of manufacture
If the transistor is placed horizontally and led out to a BL plug through the BL, then the manufacturing process is simplified, but the signal propagation speed decreases due to high contact resistance
Solution Approach 1:
The patent introduces a three-dimensional stacked architecture where bit lines are arranged in multiple vertical layers (BL0-BL3) with different extension directions. This dimensional transformation allows signal pathways to be optimized in three-dimensional space, reducing the effective contact distance and resistance between bit lines and plugs, thereby improving signal propagation speed while maintaining manufacturing feasibility through standardized layer formation processes.
3Reliability
If insulating material is filled between adjacent BLs, then the electrical isolation is improved, but the contact area between BL and BL plug is reduced
Solution Approach 1:
The patent resolves the conflict between electrical isolation and contact area by transitioning to a three-dimensional stacked structure. Bit lines in different layers (e.g., BL0-BL1 and BL2-BL3) can be positioned to overlap or adjacent to each other in the horizontal plane while being separated vertically by insulating layers. This allows insulating material to be placed between adjacent BLs in the same layer for electrical isolation, while the vertical stacking provides additional contact pathways that maintain sufficient contact area with BL plugs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces contact resistance, improves signal propagation speed, and enhances the overall performance of the semiconductor structure by achieving better ohmic contact and reducing BL resistance.
Implementation Method 1
vapor doping is used to reduce resistance, enhancing ohmic contact and increasing the contact area between the core and conductive layers
Data Source
AI summary
The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors, including: a substrate, a first stacked structure is disposed on the substrate, and the first stacked structure includes a memory cell array; a plurality of word lines (WLs), where the WL is disposed in the first stacked structure and is electrically connected to the memory cell array; a plurality of bit lines (BLs), the BL is disposed beside the first stacked structure, and is electrically connected to the memory cell array; and one end of each BL away from the memory cell array forms a step, and the BL includes a first core layer and a first conductive layer covering the first core layer; and a plurality of BL plugs, each BL plug is in corresponding contact with the first conductive layer of one of the BLs.