3D Bit Line Formation for DRAM Overlay Margin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of dynamic random access memory (DRAM) capacitors in semiconductor memory devices leads to a reduction in the overlay margin between storage node contacts (SNC) and bit lines, making it difficult to form these components effectively.
Innovation Solution
A method of manufacturing semiconductor memory devices involves forming insulation layers and conductive layers to create bit lines and storage node contacts, with specific etching and polishing processes to enhance bridge characteristics and reduce loading capacitance, while minimizing the overall height of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DRAM integration is increased, then memory capacity increases, but overlay margin between SNC and bit line decreases
Solution Approach 1:
The patent transitions from planar bit line formation to three-dimensional formation by depositing conductive layers on inclined sidewalls of insulation layers. This vertical dimension allows bit lines to extend over larger areas without increasing lateral footprint, thereby maintaining overlay margins while achieving higher integration
Solution Approach 2:
The patent forms bit lines by nesting conductive layers within and on top of insulation layer structures. The first conductive layer is deposited on the inclined sidewalls of the first insulation layer, and the second conductive layer is deposited on the inclined sidewalls of the second insulation layer, creating a nested configuration that maximizes space utilization
2Area of stationary object
If overlay margin is reduced, then device area decreases, but bridge characteristics of bit line deteriorate
Solution Approach 1:
The patent creates bridge characteristics by extending bit lines vertically along inclined sidewalls rather than relying solely on horizontal connections. This three-dimensional configuration ensures reliable electrical connection even when horizontal overlay margins are reduced
Solution Approach 2:
The patent uses composite structures combining multiple insulation layers (first and second insulation layers) with multiple conductive layers (first and second conductive layers) to form robust bit line connections. The combination of these materials creates reliable bridge characteristics through the inclined sidewall configuration
3Area of stationary object
If overlay margin is reduced, then device area decreases, but loading capacitance of bit line increases
Solution Approach 1:
The patent reduces loading capacitance by forming thinner insulation layers (first and second insulation layers) as part of the inclined sidewall structure. The reduced thickness of these layers decreases the capacitive coupling between the bit line and underlying structures, thereby reducing loading capacitance
Data Source
AI summary
Methods of forming a semiconductor include forming an insulation layer over a semiconductor substrate in which a first region and a second region are defined. A storage node contact (SNC) that passes through the insulation layer is formed and is electrically connected to the first region. A conductive layer that passes through the insulation layer is deposited and is electrically connected to the second region on the insulation layer and the SNC. A bit line is formed by removing an upper portion of the conductive layer, an upper portion of the insulation layer and an upper portion of the SNC until the SNC and the conductive layer are electrically separated from each other, wherein the bit line is a remaining part of the conductive layer.