3D Functional Block Stacking Without CMP Edge Degradation
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Solution Overview
Problem
Current 3D assembly technologies in microelectronics face challenges in scalability, edge degradation, and incompatibility issues due to chemical mechanical polishing (CMP) processes, leading to mechanical reliability concerns and complex assembly of substrates with different materials and designs.
Innovation Solution
A 3D assembly process involving planarized functional blocks with copper conductive elements, transferred by direct bonding onto a receiver substrate, allowing for multiple stacks with improved mechanical strength and reduced footprint, using a method that avoids edge effects and local erosion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP planarization is used for 3D assembly, then surface flatness is improved, but edge degradation and local erosion occur
Solution Approach 1:
The patent extracts and removes the harmful CMP planarization step from the 3D assembly process. By eliminating this process, the invention avoids the edge degradation and local erosion that CMP causes, while still achieving the necessary surface preparation through alternative means that do not induce these harmful effects.
Solution Approach 2:
The patent converts the previously harmful effect of CMP-induced edge degradation into a benefit by demonstrating that avoiding CMP entirely preserves edge integrity. The natural surface conditions, previously considered problematic, are now utilized as advantageous for maintaining edge strength and avoiding microcracks.
2Productivity
If CMP planarization is applied to multiple stacks, then integration density increases, but mechanical reliability decreases due to intra-and inter-layer microcracks
Solution Approach 1:
The patent extracts the CMP planarization process from the multi-stack assembly methodology. By removing this process step, the invention eliminates the cause of intra-and inter-layer microcracks while maintaining the ability to achieve high integration density through alternative assembly approaches that do not compromise mechanical reliability.
3Manufacturing precision
If hybrid bonding with CMP activation is used, then bonding surface quality is improved, but edge erosion and process complexity increase
Solution Approach 1:
The patent extracts and eliminates the CMP activation step from the hybrid bonding process. By removing this step, the invention simplifies the overall process while achieving adequate bonding surface quality through alternative preparation methods, thereby reducing both edge erosion and process complexity.
4Reliability
If damascene-type processes are used for 3D assembly, then interconnection reliability is improved, but edge degradation and manufacturing complexity increase
Solution Approach 1:
The patent extracts the CMP planarization step from the damascene-type processes used in 3D assembly. By removing this step, the invention maintains interconnection reliability through alternative surface preparation methods while significantly reducing manufacturing complexity and avoiding the edge degradation associated with repeated CMP cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient assembly of multiple functional blocks with enhanced integration density and performance, addressing scalability and compatibility issues while minimizing environmental impact.
Implementation Method 1
the conductive elements of the first interconnection layer of the first functional block being opposite and in contact with the conductive elements of the second interconnection layer of the second functional block
Implementation Method 2
transferring, successively, onto a receiver substrate, the functional blocks, by direct bonding
Data Source
AI summary
The present description concerns a process including the following steps: providing a plurality of assemblies, each including a donor substrate covered by a functional block successively including a first interconnection layer, a functional layer, and a second interconnection layer, the functional layer including one or more electronic components, the interconnection layers including a dielectric material in which are formed conductive elements, a first surface of the first interconnection layer in contact with the donor substrate and the free surface of the second interconnection layer being planarized so as to be compatible with a subsequent direct bonding, successively transferring, onto a receiver substrate the functional blocks, by direct bonding, to form a 3D assembly comprising a receiver substrate covered by a stack of two functional blocks.