3D Bonded Memory and Logic Stack With TSV Interconnect Reduction
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the production of custom logic families with varying products, and struggle with inter-chip interconnects, which dominate IC performance and power consumption.
Innovation Solution
The development of a 3D IC technology using Through-Silicon-Via (TSV) connections, which allows for the construction of configurable logic, memory, and analog dies with reduced interconnect size, enabling multiple connections less than one micron in size, and incorporating antifuse layers for power management and interconnection, along with layer transfer techniques for precise alignment and high-density connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If current semiconductor fabrication methods are used, then manufacturing process is established, but mask-set costs are high and flexibility is low
Solution Approach 1:
The patent segments the semiconductor fabrication process into multiple independent layers (logic die, memory die, analog die) that can be manufactured separately and then bonded together. This segmentation allows each layer to be optimized independently and enables greater flexibility in producing custom logic families without requiring complete retooling of the entire fabrication process, thereby reducing mask-set costs while improving adaptability.
Solution Approach 2:
The patent transitions from traditional planar 2D integration to 3D vertical integration by stacking multiple functional layers (logic, memory, analog) vertically. This dimensional change enables custom logic families to be produced by reconfiguring the stack composition rather than changing fabrication masks, significantly improving flexibility while reducing manufacturing costs.
2Length of moving object
If traditional inter-chip interconnects are used, then chip connections are established, but interconnect size is large and power consumption is high
Solution Approach 1:
The patent merges the interconnect function into the vertical stacking architecture itself, where Through-Silicon-Via (TSV) connections serve both as structural bonds between layers and as electrical interconnects. This integration eliminates the need for separate, large external inter-chip interconnects, reducing interconnect size and associated power consumption while maintaining connection functionality.
Solution Approach 2:
The patent moves interconnections from the horizontal plane to the vertical dimension by using Through-Silicon-Via (TSV) connections that pass vertically through the stacked layers. This vertical routing significantly shortens interconnect length compared to traditional horizontal routing, thereby reducing both interconnect size and power consumption.
3Length of moving object
If 3D IC technology with TSV connections is used, then interconnect size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the complex 3D IC manufacturing process into standardized, repeatable steps for each layer (substrate preparation, TSV formation, bonding, planarization). By breaking down the complex process into modular segments, the manufacturing complexity is managed more effectively, allowing reduced interconnect size to be achieved without overwhelming manufacturing complexity.
Solution Approach 2:
The patent creates universal, standardized processes and structures (such as standardized TSV dimensions, bonding interfaces, and layer configurations) that can be applied across different 3D IC products. This universality reduces manufacturing complexity by enabling reuse of proven processes rather than developing custom solutions for each product, thereby achieving reduced interconnect size with manageable complexity.
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; and a second level including a plurality of second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of memory cells, where each of the plurality of memory cells includes at least one of the second transistors, where the device includes at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.