3D Bonded Semiconductor Package for Shorter Memory Interconnects
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Solution Overview
Problem
The increasing size of semiconductor packages to accommodate additional memory devices and interconnects leads to reliability risks, mechanical stress, and power integrity concerns, hindering miniaturization and high-performance computing applications.
Innovation Solution
A semiconductor package structure with a first substrate, a first semiconductor die, and a first memory component, where the memory component is vertically overlapped and coupled through bonding layers, reducing interconnect length and enhancing electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If package size is increased to accommodate additional memory devices and interconnects, then memory bandwidth and storage capacity are improved, but reliability deteriorates due to increased mechanical stress and peel stress
Solution Approach 1:
The patent transitions from a two-dimensional lateral arrangement of memory devices to a three-dimensional vertical stacking architecture. Multiple memory devices are stacked vertically above the semiconductor die, enabling increased memory capacity and bandwidth without expanding the package footprint. This dimensional change eliminates the need for extended lateral interconnects, thereby reducing mechanical stress and peel stress while maintaining high memory bandwidth and storage capacity.
2Quantity of substance
If package size is increased to accommodate additional memory devices, then memory capacity is improved, but manufacturing yield deteriorates due to reduced confidence in assembly yield
Solution Approach 1:
By stacking memory devices vertically in the Z-dimension rather than arranging them laterally, the patent achieves high memory capacity within a compact footprint. This vertical integration simplifies the assembly process and reduces the complexity of interconnect routing, thereby improving manufacturing yield and assembly confidence while maintaining high memory capacity.
3Adaptability or versatility
If extended routing paths are used through LSI or bridge die, then connectivity between semiconductor die and memory devices is achieved, but power integrity deteriorates due to additional resistance, inductance, and parasitic effects
Solution Approach 1:
The patent eliminates the intermediate LSI or bridge die that were previously required for routing connections between the semiconductor die and memory devices. By directly coupling the memory devices to the semiconductor die through vertical interconnects, the patent removes the extended routing paths that introduced additional resistance, inductance, and parasitic effects, thereby improving power integrity while maintaining connectivity.
4Adaptability or versatility
If LSI or bridge die is used for routing, then interconnect functionality is achieved, but mechanical reliability deteriorates due to susceptibility to mechanical breakage
Solution Approach 1:
The patent removes the LSI or bridge die from the package structure, eliminating the mechanical breakage risks associated with these intermediate components. Direct vertical interconnects are established between the semiconductor die and memory devices, providing robust mechanical reliability while maintaining full interconnect functionality through simplified routing.
5Quantity of substance
If package size is increased, then memory bandwidth is improved, but mechanical stress deteriorates due to higher peel stress
Solution Approach 1:
The patent achieves high memory bandwidth through vertical stacking in the Z-dimension rather than lateral expansion. This dimensional change concentrates the interconnect paths directly above the semiconductor die, minimizing the area subject to peel stress and reducing mechanical stress while maintaining high memory bandwidth through shortened signal paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves electrical performance by lowering signal delay and enhancing power integrity while reducing package footprint and increasing memory bandwidth and storage.
Implementation Method 1
The first memory component is coupled to the first semiconductor die through a first connection structure formed by the first bonding layer and the second bonding layer
Data Source
AI summary
A semiconductor package structure is provided. The semiconductor package structure includes a first substrate, a first semiconductor die, and a first memory component. The first semiconductor die is disposed over the first substrate and has a first surface adjacent to the first substrate and a second surface away from the first substrate. The first semiconductor die includes a first bonding layer disposed on the second surface of the first semiconductor die. The first memory component is disposed over the first semiconductor die. The first memory component vertically overlaps the first semiconductor die. The first memory component includes a second bonding layer adjacent to the second surface of the first semiconductor die. The first memory component is coupled to the first semiconductor die through a first connection structure formed by the first bonding layer and the second bonding layer.