3D Semiconductor Bonding Structure for Dense Interlayer Connections
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the production of commercially viable logic families with diverse products, and existing 3D IC technologies are constrained by large Through-Silicon Vias (TSVs) that restrict the number of connections that can be made.
Innovation Solution
The development of a 3D IC device fabrication method using a re-programmable antifuse in conjunction with Through Silicon Via (TSV) technology to construct configurable logic, allowing for the creation of multiple layers with smaller interconnects, enabling a modular approach to build various configurable systems and reducing the need for multiple mask sets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Through-Silicon Vias (TSVs) are used to connect layers in 3D ICs, then vertical interconnect is achieved, but the large size of TSVs restricts the number of connections that can be made
Solution Approach 1:
The patent segments the interconnect structure into multiple components: smaller TSVs for vertical connection, bonding pads on intermediate layers, and redistribution layers. This segmentation allows multiple smaller connections instead of fewer large TSVs, increasing the total number of connections while reducing individual interconnect size
Solution Approach 2:
The patent introduces intermediate bonding layers between the first and second levels, creating an additional dimensional plane for connections. This allows connections to be made at multiple vertical positions rather than requiring all connections to pass through single large TSVs, thereby increasing connection density
2Adaptability or versatility
If conventional 2D IC fabrication methods are used, then manufacturing process is established, but high mask-set costs and low flexibility limit production of diverse products
Solution Approach 1:
The patent forms bonding pads and prepares interconnect structures on intermediate layers before final assembly. This preliminary action allows configuration changes to be made at the bonding/assembly stage rather than requiring new mask sets for each product variant, enabling cost-effective production of diverse products
Solution Approach 2:
The patent creates a re-programmable logic family where the logic function can be configured after fabrication through programming of the logic cells. This dynamic configurability allows a single fabricated structure to serve multiple product purposes, increasing adaptability without requiring multiple fabrication mask sets
3Reliability
If directly bonded levels with metal to metal bonds are used, then inter-layer connectivity is achieved, but inter-chip interconnect impact must be managed
Solution Approach 1:
The patent introduces bonding pads as intermediary elements between the metal layers of different levels. These bonding pads serve as buffered connection points that manage the mechanical and electrical stress of direct bonding, ensuring reliable connectivity while isolating the impact of inter-chip interconnects
Solution Approach 2:
The patent creates localized bonding pad regions with specific material properties and geometries optimized for bonding. By concentrating connection functions in these localized areas with enhanced properties, the patent achieves reliable connectivity while containing and managing the harmful effects of inter-chip interconnects in specific locations rather than across the entire structure
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.