3D Semiconductor Bonding Structure With Inverted Front-Back Stacking
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Solution Overview
Problem
The semiconductor industry faces challenges in further increasing circuit density due to process limitations in shrinking minimum feature sizes, and existing 3D integrated circuit stacking and bonding technologies face manufacturing difficulties as more IC dies are bonded together.
Innovation Solution
The development of a manufacturing method for semiconductor structures that includes a front-to-back bonding interface, involving stages such as wafer preparation, thinning, formation of bonding vias and structures, and bonding processes to stack and connect IC dies efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 3D integrated circuit stacking and bonding technologies are used to increase circuit density, then more IC dies can be bonded together, but manufacturing challenges and process complexity increase significantly
Solution Approach 1:
The patent inverts the conventional bonding sequence by performing back-side bonding before front-side bonding. This reversal simplifies the manufacturing process by enabling earlier substrate thinning and eliminating the need for complex alignment and handling procedures associated with front-side first bonding, thereby reducing overall process complexity while achieving high circuit density through multi-die stacking
2Quantity of substance
If more IC dies are bonded together to increase integration density, then circuit functionality is enhanced, but reliability of bonding interfaces becomes more difficult to ensure
Solution Approach 1:
The patent performs preliminary surface preparation, bonding pad formation, and alignment feature creation on the back side of substrates before the actual bonding process. This preliminary action on the back side ensures that bonding interfaces are properly prepared and aligned before front-side bonding, enhancing reliability of bonding interfaces while enabling higher integration density through multiple die stacking
Data Source
AI summary
A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes top, bottom, and middle tiers. The bottom tier includes a first interconnect structure overlying a first semiconductor substrate, and a first front-side bonding structure overlying the first interconnect structure. The middle tier interposed between and electrically coupled to the top and bottom tiers includes a second interconnect structure overlying a second semiconductor substrate, a second front-side bonding structure interposed between the top tier and the second interconnect structure, and a back-side bonding structure interposed between the second semiconductor substrate and the first front-side bonding structure. A bonding feature of the second front-side bonding structure includes a first bonding via in contact with the second interconnect structure, a first bonding contact overlying the first bonding via, and a barrier layer interface between a bottom of the first bonding contact and a top of the first bonding via.