3D Semiconductor Bonding Structure With Programmable Vertical Interconnects
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the production of commercially viable logic families with diverse products, and existing 3D IC technologies are constrained by large Through-Silicon Vias (TSVs) that restrict the number of connections due to their size.
Innovation Solution
The development of a 3D IC device fabrication method using layer transfer technology and Through-Silicon Vias (TSVs) with antifuse programmable interconnects, allowing for the construction of configurable logic, memory, and analog functions with reduced interconnect size and increased connectivity, enabling the creation of modular systems with mixed-process dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If Through-Silicon Vias (TSVs) are used for interconnect in 3D ICs, then vertical connections between layers are enabled, but the large size of TSVs restricts the number of connections
Solution Approach 1:
The patent segments the interconnect function by introducing antifuse programmable interconnects that can be selectively activated. Instead of requiring all possible TSV connections to be physically present, the system uses a subset of TSVs combined with programmable antifuse elements to achieve the desired connectivity. This segmentation allows fewer, smaller TSVs to provide equivalent or superior connection density compared to traditional approaches requiring numerous large TSVs.
Solution Approach 2:
The patent changes the operational parameters of the interconnect system by introducing programmability through antifuse elements. The interconnect structure transitions from a fixed physical configuration to a dynamically configurable state, where connections are established through programming rather than solely through physical presence. This parameter change enables smaller TSV dimensions while maintaining high connectivity density through software-controlled connection establishment.
2Adaptability or versatility
If conventional fabrication methods are used, then manufacturing process is established, but mask-set costs are high and flexibility is low
Solution Approach 1:
The patent implements universality through antifuse programmable interconnects that can be configured to perform multiple different connection functions using the same physical infrastructure. A single fabrication process can produce devices with different interconnect configurations by simply changing the programming patterns, rather than requiring different mask sets for each product variant. This multi-functionality enables high product diversity while maintaining cost-effective manufacturing through process reuse.
Solution Approach 2:
The patent applies preliminary action by pre-configuring the antifuse elements during fabrication to establish potential connection paths, which are then selectively activated through programming. The physical interconnect structure is prepared in advance with all necessary components in place, and the specific connection topology is determined later through programming. This separates the expensive fabrication step from the flexible configuration step, reducing mask-set costs while enabling product diversity.
3Productivity
If TSV size is reduced to increase connection density, then more connections can be made, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces antifuse elements as intermediary components between the TSV physical structure and the logical connection function. Rather than relying solely on precise TSV alignment and dimensions, the antifuse elements act as mediators that can compensate for manufacturing variations. This intermediary layer allows larger tolerances in TSV fabrication while still achieving high connection density through the programmable selection and activation of connection paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, enhances flexibility in producing various logic families, and enables a higher density of connections in 3D ICs, overcoming the limitations of traditional TSVs by allowing for multiple connections less than one micron in size, thus expanding the applicability of 3D IC technology.
Implementation Method 1
the bonded includes direct oxide-to-oxide bonds
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the at least one of the second transistors transistor channel includes non-silicon atoms, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.