3D Stacked Capacitance Structure With Etch-Stop Thickness Control
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Solution Overview
Problem
The limitation of single capacitors in chiplets to high capacitance due to manufacturing on a silicon substrate hinders the increase in capacitance, which is a bottleneck in achieving higher transistor density and performance at a relatively low cost.
Innovation Solution
A 3D capacitance structure is formed by stacking sub-capacitance structures with electrode contacts, utilizing dielectric and electrode layers with etching stop layers to control thickness and connect layers directly, enabling a multi-layer structure with increased capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single capacitor is manufactured on a silicon substrate in chiplet, then the manufacturing process is simple, but the capacitance is limited and cannot be increased
Solution Approach 1:
The patent transitions from planar 2D capacitor structures to vertical 3D stacked capacitor structures. Multiple capacitor layers are stacked vertically along the thickness direction of the substrate, enabling capacitance multiplication without increasing the planar footprint. This dimensional transition resolves the contradiction by achieving higher capacitance through vertical stacking while maintaining compact form factor.
Solution Approach 2:
The capacitor structure is segmented into multiple discrete layers including first and second electrode plates, dielectric layers, and conductive plugs arranged in separate stacked layers. Each capacitor layer can be independently formed and controlled, allowing the overall capacitance to be increased by adding more segmented layers without proportionally increasing manufacturing complexity.
2Quantity of substance
If multi-layer capacitor structure is formed to increase capacitance, then the capacitance increases, but the layer thickness control becomes difficult
Solution Approach 1:
Etching stop layers are introduced as intermediary layers between the dielectric layers and electrode plates. These stop layers serve as precise thickness reference markers during the etching process, enabling accurate control of layer thicknesses. The etching stop layers are selectively removed to define the thickness of adjacent dielectric and conductive layers, providing a mediator that simplifies thickness control in the multi-layer stacked structure.
Solution Approach 2:
The etching stop layers are formed in advance before the final electrode and dielectric layer deposition. By pre-establishing these reference layers, the subsequent manufacturing steps can use them as guides for achieving precise thickness control, rather than attempting to control thickness through complex real-time adjustments during layer formation.
3Quantity of substance
If vertical electrode contacts are used to connect stacked capacitor layers, then the capacitance increases, but the structure stability decreases
Solution Approach 1:
The patent merges the electrode contacts with the capacitor electrode plates by forming continuous conductive structures that extend vertically through multiple layers. The first and second electrode plates are connected through conductive plugs that are integrated with the electrode structures themselves, creating a unified and stable conductive pathway. This merging eliminates separate contact structures that could compromise stability while maintaining the vertical stacking needed for increased capacitance.
Data Source
AI summary
A 3D capacitance structure, including multiple sub-capacitance stack structures, multiple first electrode contacts, and multiple second electrode contacts, is provided. Each sub-capacitance stack structure includes a dielectric stack, a lower electrode structure, and an upper electrode structure. The dielectric stack includes a stack of dielectric layers and etching stop layers. The lower electrode structure includes a lower electrode plate disposed in a lower dielectric layer and multiple lower electrode extended portions passing upward from the lower electrode plate through a lower etching stop layer to an intermediate dielectric layer. The upper electrode structure includes an upper electrode plate disposed in an upper dielectric layer and multiple upper electrode extended portions extending downward from the upper electrode plate to the lower etching stop layer. The first electrode contacts and the second electrode contacts are respectively connected to lower and upper electrode plates of two adjacent layers in the sub-capacitance stack structures.