3D Capacitive Transistor Gate Layout for Compact High-Voltage ICs
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Solution Overview
Problem
Integrated circuits with planar capacitive transistors used for high-voltage operations are bulky due to their large size, requiring significant space and increasing the overall dimensions of the circuit, which is a challenge for reducing the bulk and cost of manufacturing.
Innovation Solution
The integration of capacitive transistors with a gate structure that extends in depth into the semiconductor substrate, combined with a dielectric layer, allowing for increased surface capacitance without expanding the physical size, enabling a reduction in the area occupied by high-voltage components by 30% to 50%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar capacitive transistors are used for high-voltage operations, then the circuit can operate at high voltages, but the area occupied by high-voltage components increases significantly
Solution Approach 1:
The gate structure transitions from a planar configuration to a three-dimensional structure that extends vertically into the semiconductor substrate. The gate comprises a first portion extending in depth into the substrate and a second portion extending over the substrate, creating a T-shaped or L-shaped vertical profile that increases capacitance without expanding the lateral footprint of the device.
Solution Approach 2:
The gate structure is nested within the semiconductor substrate by extending the first portion of the gate vertically into the substrate. This nested configuration allows the capacitive element to utilize the vertical dimension of the substrate, effectively increasing the capacitance density by nesting the gate structure within the available substrate volume rather than expanding laterally.
2Reliability
If the gate extends deeper into the semiconductor substrate, then the surface capacitance increases, but the manufacturing complexity increases
Solution Approach 1:
The gate is segmented into two distinct portions: a first portion that extends vertically into the semiconductor substrate and a second portion that extends horizontally over the substrate. This segmentation allows each portion to be optimized independently for its specific function while simplifying the overall manufacturing process by breaking down the complex three-dimensional structure into manageable fabrication stages.
Solution Approach 2:
Different portions of the gate structure have different geometries and orientations optimized for their local functions. The first portion extending into the substrate provides vertical capacitance, while the second portion extending over the substrate provides horizontal connectivity. This local optimization of structure and quality allows the device to achieve high capacitance without uniform complexity throughout the entire structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a more compact integrated circuit design, reducing manufacturing costs and enabling more circuits to be produced from the same semiconductor wafer while maintaining high-voltage operation capabilities.
Implementation Method 1
a dielectric layer extending between the gate and the semiconductor substrate
Implementation Method 2
the capacitive transistor has a surface capacitive value which depends on the length over which its first portion extends in depth in the semiconductor substrate
Data Source
AI summary
An integrated circuit includes a capacitive transistor supported by a semiconductor substrate. The capacitive transistor includes: a drain and a source formed in the semiconductor substrate; a gate having a first portion extending in depth in the semiconductor substrate, and a second portion prolonging said first portion and extending over the semiconductor substrate; and a dielectric layer extending between the gate and the semiconductor substrate.