3D Capacitor Array Layout for Compact Voltage Regulator Packaging
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Solution Overview
Problem
The challenge of downsizing semiconductor devices while maintaining a short connection distance from capacitors to loads is hindered by the need for increased mounting area and longer wiring distances, leading to higher equivalent series inductance (ESL) and resistance (ESR) losses.
Innovation Solution
The integration of an integrally formed capacitor array with through hole conductors in the wiring board, allowing capacitors to overlap the load and reducing the need for planar wiring, thus minimizing the device size and connection distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitors are disposed on one mounting surface of the wiring board for individual channels, then the voltage regulation function is achieved, but the mounting area increases and the device size cannot be downsized
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional arrangement by having capacitors extend in the thickness direction of the wiring board. The capacitors are disposed to overlap with the mounting surface, utilizing the vertical dimension rather than only the horizontal plane. This allows multiple capacitors for multiple channels to be arranged within a smaller footprint area while maintaining all necessary electrical connections through the wiring board's conductive structures.
2Reliability
If capacitors are disposed for individual channels, then each channel gets proper decoupling, but the mounting area increases as the number of channels increases
Solution Approach 1:
The patent merges multiple capacitor functions into a compact three-dimensional arrangement where capacitors for different channels are vertically stacked and overlap each other. The wiring board's internal conductive layers and via structures are used to provide separate electrical connections to each capacitor, allowing multiple decoupling functions to coexist in a unified, space-efficient configuration rather than requiring separate planar areas for each channel's capacitor.
3Ease of manufacture
If connection distance from capacitor to load increases, then wiring layout becomes easier, but loss caused by equivalent series inductance and resistance increases
Solution Approach 1:
The patent optimizes the local electrical connection quality by providing direct, short-distance connections between capacitors and the load through the wiring board's internal conductive structures. The via holes and conductive patterns are strategically positioned to minimize the path length from capacitor terminals to load terminals, ensuring low ESL and ESR. This local optimization of connection quality allows the capacitors to be positioned closer to the load without compromising manufacturing ease.
Data Source
AI summary
A semiconductor composite device includes active elements and passive elements constituting a voltage regulator and disposed in association with a plurality of channels, a load to be supplied with a direct-current voltage regulated by the voltage regulator, and a wiring board electrically connected to the active elements, the passive elements, and the load. A plurality of capacitors disposed in the channels include an integrally formed capacitor array including a plurality of capacitor portions disposed in a plane. The capacitor array includes a plurality of through hole conductors extending through the capacitor array in a direction perpendicular to a mounting surface of the wiring board. At least a part of the capacitor array is positioned to overlap the load when viewed from the mounting surface of the wiring board.