3D Capacitor Architecture for BEOL Space-Limited Semiconductors
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Solution Overview
Problem
Current capacitors in semiconductor devices have limited capacity and power density due to their fabrication within the backend interconnect structure, which has limited layout spaces, and the thermal budget restrictions of the BEOL process.
Innovation Solution
The development of three-dimensional capacitors with a corrugated structure and integration of high-efficiency solid-state electrolytes, enabling the formation of electric double layer capacitors or Redox faradaic reaction based pseudocapacitor arrays, which can be vertically integrated into a 3D interposer or the backside of a processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If capacitors are fabricated within the backend interconnect structure, then the device can be integrated into the existing BEOL process, but the layout space is limited leading to insufficient power density and capacitance capacity
Solution Approach 1:
The patent transitions from planar 2D capacitor layouts to three-dimensional vertical capacitor structures. Multiple capacitor units are stacked vertically around a central pole, utilizing the third dimension (height) to increase capacitance capacity without occupying additional lateral layout space. This vertical stacking approach resolves the contradiction by maintaining BEOL integration while dramatically increasing the quantity of capacitive material.
Solution Approach 2:
The patent implements a nested configuration where capacitor units are arranged concentrically around a central pole. Each capacitor unit consists of an electrode, dielectric layer, and optional solid-state electrolyte layer, with these layers nested around the pole in a doll-like configuration. This nesting approach maximizes the use of vertical space and increases capacitance capacity within the constrained BEOL layout.
2Ease of manufacture
If conventional capacitor structures are used in BEOL, then the fabrication process is simpler, but the power density is insufficient for modern processor requirements
Solution Approach 1:
The patent employs composite material structures combining multiple functional layers: conductive electrodes, high-k dielectric materials, and solid-state electrolytes. This composite approach increases power density by utilizing materials with superior electrical properties while maintaining compatibility with BEOL fabrication processes. The combination of different material types allows the capacitor to achieve higher capacitance per unit volume.
Solution Approach 2:
The patent applies local quality optimization by selectively placing different materials and structures in specific regions of the capacitor. The central pole, electrode layers, dielectric layers, and solid-state electrolyte layers are positioned to maximize local electric field strength and capacitance density. This localized optimization of material properties and structural configuration enhances overall power density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the power density and information storage capacity of capacitors, allowing processors to operate at improved frequencies even when running on battery, and enabling remote operation without a wired power source.
Implementation Method 1
integration of high-efficiency solid-state electrolytes, enabling the formation of electric double layer capacitors
Implementation Method 2
integration of high-efficiency solid-state electrolytes, enabling the formation of Redox faradaic reaction based pseudocapacitor arrays
Data Source
AI summary
Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.