3D Transistor Capacitor Cell Layout for Higher Capacitance Density
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Solution Overview
Problem
Semiconductor integrated circuit devices using three-dimensional transistor devices face challenges in implementing capacitor cells with high capacitance values per unit area, which affects noise resistance and performance due to increased operating frequency and decreased operating voltage.
Innovation Solution
The design incorporates a capacitor cell with a three-dimensional transistor device, featuring longer local interconnects that protrude from the diffusion layer to increase parasitic capacitance, and utilizes double patterning to form metal interconnects with different masks, allowing for closer spacing and higher capacitance values per unit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the local interconnect is extended to protrude further from the power supply interconnect, then the capacitance value per unit area is improved, but the device area is increased
Solution Approach 1:
The patent utilizes the vertical dimension by extending the local interconnect in the second direction (vertical/protruding direction) rather than only in the planar direction. This allows the interconnect to protrude from the diffusion layer surface, creating additional capacitance through increased overlap with the gate interconnect in the vertical dimension while minimizing planar area occupation.
Solution Approach 2:
The local interconnect is nested within the capacitor cell structure, extending from the diffusion layer toward the gate interconnect. This nesting arrangement allows the interconnect to be positioned optimally for capacitance formation while sharing space within the existing cell boundaries, effectively utilizing the vertical space between layers.
2Reliability
If the local interconnect is extended to increase parasitic capacitance, then the noise resistance is improved, but the manufacturing precision is worsened
Solution Approach 1:
The patent changes the geometric parameters of the local interconnect, specifically extending its length in the second direction to increase parasitic capacitance. By controlling this dimensional parameter, the design achieves enhanced noise resistance while the manufacturing process maintains precision through standard photolithography and etching techniques that can reproduce the extended geometry.
Solution Approach 2:
The extended local interconnect serves dual purposes: it provides electrical connection functionality while simultaneously generating parasitic capacitance for noise suppression. This self-service approach allows the same structural element to fulfill both interconnection and noise resistance requirements without requiring separate dedicated components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the capacitance value of capacitor cells per unit area, enhancing the noise resistance and performance of semiconductor integrated circuit devices by optimizing the layout and interconnect configuration.
Implementation Method 1
increasing parasitic capacitance between the local interconnects and the gate interconnects
Data Source
AI summary
The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.