3D Capacitor Electrode Structure for Stable Low-Frequency Displays

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Solution Overview

Problem

Display apparatuses face challenges in achieving improved display quality due to limitations in pixel control and capacitance design, particularly in reducing IR interference and increasing capacitance density within a limited area.

Innovation Solution

The display apparatus incorporates a substrate with specific semiconductor and conductive layers, including a driving unit transistor and capacitors, utilizing silicon and oxide semiconductor materials, and a unique capacitor electrode structure to enhance pixel control and capacitance, reducing IR interference and increasing capacitance density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a conventional capacitor structure is used, then the manufacturing process is simple, but the capacitance density is insufficient

Engineering Contradiction:
Improvecapacitance densityVSAvoidcapacitor structure complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from a planar capacitor structure to a three-dimensional stacked structure by introducing a third capacitor electrode above the first and second capacitor electrodes. This vertical stacking arrangement increases the effective capacitance area without expanding the lateral footprint, thereby achieving higher capacitance density within the same pixel area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested capacitor configuration where the first capacitor electrode, second capacitor electrode, and third capacitor electrode are arranged in overlapping layers. The third capacitor electrode is positioned above and overlaps with both the first and second capacitor electrodes, creating a nested structure that maximizes capacitance within a compact volume.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Illumination intensity

If the pixel area is increased to improve display quality, then the display quality improves, but the IR interference increases

Engineering Contradiction:
Improvedisplay qualityVSAvoidIR interference
Core Design Contradiction:
Illumination intensityVSObject-affected harmful factors

Solution Approach 1:

By stacking capacitor electrodes vertically, the patent achieves higher capacitance density without increasing the lateral pixel area. This allows the pixel to maintain its original size and thus avoid increased IR interference while still achieving improved display quality through enhanced capacitance performance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If more capacitor electrodes are added to increase capacitance, then the capacitance density increases, but the manufacturing complexity increases

Engineering Contradiction:
Improvecapacitance densityVSAvoidmanufacturing process complexity
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The third capacitor electrode serves multiple functions: it forms capacitance with both the first capacitor electrode (creating a first capacitor) and the second capacitor electrode (creating a second capacitor). This multi-functional design increases capacitance density without proportionally increasing manufacturing complexity, as a single additional electrode layer achieves multiple capacitance objectives.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP4435861A1Display apparatus
Publication Date: 2024.09.25 SAMSUNG DISPLAY CO LTD
  • EP4435861A1 patent drawingFigure 1A
  • EP4435861A1 patent drawingFigure 1B
  • EP4435861A1 patent drawingFigure 2

AI summary

A display apparatus includes a substrate including a display area and a peripheral area, a first semiconductor layer including a driving unit semiconductor pattern, a first conductive layer disposed on the first semiconductor layer, and including a first capacitor electrode and a second capacitor electrode, a second conductive layer disposed on the first conductive layer, and including a third capacitor electrode overlapping the first capacitor electrode and the second capacitor electrode, a second semiconductor layer disposed on the second conductive layer, and including a first semiconductor pattern overlapping the third capacitor electrode, a third conductive layer disposed on the second semiconductor layer, and including a first electrode pattern overlapping the first semiconductor pattern and the third capacitor electrode, and a fourth conductive layer disposed on the third conductive layer, and including a connection electrode electrically connected to the first semiconductor pattern and the third capacitor electrode.