3D Capacitor Electrode Structure for High-Density Reliability
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Solution Overview
Problem
The challenge in semiconductor devices is to enhance electrical properties and reliability, particularly in capacitors, while maintaining miniaturization and high integration density, which existing designs struggle to achieve effectively.
Innovation Solution
The semiconductor device incorporates a unique capacitor structure with a first and second lower electrode configuration, where the second lower electrode protrudes above the supporter layer, and a dielectric layer is used between the electrodes, along with supporter layers to support the electrodes and increase capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the capacitor size is miniaturized to achieve high integration density, then the integration density is improved, but the electrical properties and reliability deteriorate
Solution Approach 1:
The lower electrode is divided into a first lower electrode and a second lower electrode that are stacked vertically. This segmentation allows the capacitor to maintain sufficient electrode surface area for good electrical properties while reducing the lateral footprint, thereby achieving miniaturization without sacrificing reliability.
Solution Approach 2:
The patent transitions from a planar capacitor structure to a three-dimensional stacked structure by placing the second lower electrode above the first lower electrode. This dimensional change enables the capacitor to store more charge (higher capacitance) within a smaller planar area, improving integration density while maintaining electrical performance.
2Volume of moving object
If the capacitor size is reduced for miniaturization, then the device size is decreased, but the capacitance and electrical properties worsen
Solution Approach 1:
The second lower electrode is positioned to surround or enclose portions of the first lower electrode, creating a nested configuration. This nesting allows both electrodes to contribute to the capacitance within a compact volume, maintaining high capacitance while achieving miniaturization.
Solution Approach 2:
By stacking the second lower electrode above the first lower electrode in the vertical dimension, the patent increases the effective electrode surface area without increasing the planar footprint. This dimensional transition enables the capacitor to maintain high capacitance while reducing overall device size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves electrical properties and reliability by increasing capacitance and maintaining miniaturization, addressing the limitations of existing designs.
Implementation Method 1
a dielectric layer on the plurality of lower electrodes and the at least one supporter layer; and an upper electrode on the dielectric layer
Implementation Method 2
a dielectric layer on the plurality of lower electrodes and the at least one supporter layer
Implementation Method 3
at least one supporter layer in contact with the plurality of lower electrodes
Data Source
AI summary
A semiconductor device may include a substrate; a plurality of lower electrodes on the substrate; at least one supporter layer in contact with the plurality of lower electrodes; a dielectric layer on the plurality of lower electrodes and the at least one supporter layer; and an upper electrode on the dielectric layer. Each of the plurality of lower electrodes may include a first lower electrode and a second lower electrode on the first lower electrode. The at least one supporter layer may include a first supporter layer in contact with a side surface of an upper region of the first lower electrode. A level of an uppermost end of the second lower electrode may be higher than a level of an upper surface of the first supporter layer.