3D Capacitor Fin Structure for Fin Width Mismatch in FinFET Integration
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Solution Overview
Problem
Existing capacitors for 3D devices face challenges in fabrication and design, particularly in integrating 3D capacitors with FinFET devices due to width mismatches and inconsistent dielectric layer thickness, leading to high etching rates and performance issues.
Innovation Solution
The design involves forming fins with different widths for 3D capacitors and FinFET devices, where the 3D capacitor fins are wider than FinFET fins, compensating for consumption during manufacturing, and using a method that includes ion implantation and thermal processing to enhance capacitance without affecting FinFET performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fins with different widths are formed for 3D capacitors and FinFET devices, then capacitance of 3D capacitors is increased and width mismatches are mitigated, but device complexity and manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by forming first fins with a first width for 3D capacitors and second fins with a second width for FinFET devices in different regions of the substrate. This allows each region to have optimized fin dimensions tailored to its specific functional requirements, enabling the 3D capacitor region to achieve higher capacitance while the FinFET region maintains appropriate device characteristics.
Solution Approach 2:
The substrate is segmented into different regions with different fin configurations. First fins are formed in a first region for 3D capacitors, while second fins are formed in a second region for FinFET devices. This segmentation allows independent optimization of fin widths for different device types, resolving the width mismatch issue while accommodating diverse functional requirements across the chip.
2Quantity of substance
If ion implantation is performed to enhance capacitance, then capacitance of 3D capacitors increases, but manufacturing process complexity increases
Solution Approach 1:
Ion implantation is performed as a preliminary action to modify the electrical properties of the first fins before subsequent capacitor formation steps. By pre-doping the first fins with appropriate ion species and concentrations, the patent enhances the capacitance of the 3D capacitors and establishes the desired electrical characteristics early in the manufacturing process, simplifying later processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the capacitance of 3D capacitors while maintaining the performance of FinFET devices, mitigating width mismatches and dielectric thickness inconsistencies, and is compatible with front-end-of-line manufacturing processes.
Implementation Method 1
A first ion implantation is performed to implant first dopants into the first fins
Implementation Method 2
thermal processing to enhance capacitance
Data Source
AI summary
A method for forming a semiconductor structure includes following operations. First fins are formed in a first region of a substrate, and second fins are formed in a second region of the substrate. Widths of the first fins are greater than widths of the second fins. An isolation structure is formed over the substrate. A first ion implantation is performed on the first fins. A portion of the isolation structure is removed to expose a portion of each first fin and a portion of each second fin. The widths of the first fins are equal to or less than the widths of the second fins after the removing of the portion of the isolation structure. A 3D capacitor is formed in the first region, and a FinFET device is formed in the second region. The 3D capacitor includes the first fins, and the FinFET device includes the second fins.