3D Capacitor Structure for FinFET Integration Without Extra Lithography
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Solution Overview
Problem
Existing capacitors for 3D devices in semiconductor manufacturing are inadequate in terms of capacitance and integration with FinFET and high voltage transistors, requiring additional photolithography steps.
Innovation Solution
A 3D capacitor design that integrates with FinFET devices and high voltage transistors without additional photolithography, utilizing a metal-insulator-metal or metal-insulator-semiconductor structure, with increased capacitance from sidewall areas, and a method for forming this structure through a series of fabrication operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing capacitor designs are used for 3D devices, then manufacturing processes are simpler, but capacitance is insufficient and additional photolithography steps are required
Solution Approach 1:
The patent merges the capacitor formation process with the existing FinFET transistor manufacturing process. The same mandrel structure is used to define both the FinFET fins and the capacitor regions, and the same dielectric layer deposition and metal electrode formation steps are used for both devices. This integration eliminates the need for separate photolithography steps for capacitor patterning, thereby increasing capacitance reliability while avoiding additional manufacturing complexity
Solution Approach 2:
The patent creates a universal manufacturing process that serves multiple functions: the mandrel structure simultaneously defines the FinFET fin regions and the capacitor regions, and the subsequent processing steps (dielectric layer deposition, metal electrode formation) serve both the transistor and capacitor fabrication. This multi-functional approach ensures sufficient capacitance is achieved through integrated design while maintaining manufacturing process simplicity
2Adaptability or versatility
If additional photolithography steps are added to improve capacitor integration, then integration with FinFET and high voltage transistors improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines the capacitor integration process with the standard FinFET manufacturing flow by using the same mandrel-based patterning approach. The mandrel is formed first, then fins are etched around it, and capacitors are formed in the same regions using identical dielectric and metal deposition steps. This merging of processes achieves full integration capability with FinFET and high voltage transistors without requiring any additional photolithography steps, thereby maintaining manufacturing efficiency
3Reliability
If capacitor size is increased to improve capacitance, then capacitance increases, but device area increases and scaling is limited
Solution Approach 1:
The patent transitions from planar capacitor geometry to a three-dimensional structure by forming metal electrodes above and below the dielectric layer that conforms to the mandrel sidewalls. This vertical stacking in the third dimension (above and below the substrate plane) dramatically increases the effective capacitance area without increasing the lateral footprint on the chip, enabling continued scaling while maintaining sufficient capacitance
Solution Approach 2:
The patent implements a nested structure where the dielectric layer is conformally deposited around the mandrel sidewalls, and metal electrodes are deposited both above and below the dielectric layer. The capacitor structure is essentially nested within the vertical space defined by the mandrel, maximizing the use of vertical space for capacitance while minimizing lateral area consumption, thus resolving the contradiction between capacitance and device area
Data Source
AI summary
A semiconductor 3D capacitor includes a semiconductor electrode disposed in a semiconductor substrate, a metal electrode over the semiconductor electrode, and an isolation structure between the semiconductor electrode and the metal electrode. The isolation structure includes a dielectric feature between the semiconductor electrode and the metal electrode, and a dielectric layer between the dielectric feature and the metal electrode. A bottom surface of the metal electrode is between a topmost surface of the dielectric feature and a bottom surface of the dielectric feature in a direction perpendicular to a surface of the semiconductor substrate.