3D Interconnect Capacitor Layout for Miniaturized Image Sensors
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Solution Overview
Problem
The miniaturization of pixel circuits in image sensors reduces the available space for capacitors, leading to lower capacitance and reduced performance due to constraints in lateral and vertical dimensions, necessitating a solution to enhance charge retention and conversion gain while maintaining or reducing the pixel circuit size.
Innovation Solution
A capacitor design that extends from a first lower contact layer on the substrate to a first upper contact layer at a first bonding layer, with the bottom electrode directly coupled to a doped region and the top electrode extending above the interconnect structure, increasing the capacitor's height and capacitance without adding additional metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the pixel circuit size is reduced for miniaturization, then the device dimensions are reduced, but the capacitor capacitance decreases and performance deteriorates
Solution Approach 1:
The capacitor is designed to extend vertically through multiple interconnect layers (from first lower contact layer through second upper contact layer), transforming a two-dimensional planar capacitor into a three-dimensional stacked structure. This vertical dimensionality change allows the capacitor to achieve sufficient capacitance in miniaturized pixel circuits without increasing lateral footprint, directly resolving the contradiction between reduced pixel size and maintained capacitor performance
2Reliability
If additional metal layers are added to increase capacitor capacitance, then the capacitance increases, but the device complexity and manufacturing cost increase
Solution Approach 1:
Existing interconnect metal layers are designed to serve dual purposes: their primary function for signal routing and their secondary function as capacitor electrodes. The first lower contact layer, first upper contact layer, second lower contact layer, and second upper contact layer all serve as both interconnect structures and capacitor plates, eliminating the need for dedicated capacitor metal layers and reducing overall device complexity
Solution Approach 2:
The capacitor structure is merged with the interconnect structure by using the same metal layers for both purposes. The capacitor electrodes are formed using existing interconnect metal layers, and the capacitor occupies vertical space within the interconnect stack, combining two functional elements into a unified structure that reduces manufacturing steps and material requirements
Data Source
AI summary
Some embodiments relate to an integrated device, including: a substrate including a first doped region; an interconnect structure on the substrate and including a plurality of wire levels and via levels; a first lower contact layer extending between the substrate and the interconnect structure; a first bonding layer over the interconnect structure; a first upper contact layer extending between the interconnect structure and the first bonding layer; a capacitor in the interconnect structure, wherein the capacitor extends above an uppermost wire level of the plurality of wire levels and via levels.