3D Capacitor Structure Matrix Grids

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Solution Overview

Problem

Existing inter-digitated capacitor structures have high resistance and require improved matching, which affects their performance in integrated circuits despite offering better capacitance compared to conventional MIM structures.

Innovation Solution

A three-dimensional capacitor structure is designed with a first and second conductive layer divided into grid units, featuring conductive grids and square holes with central islands, and a plug layer connecting them, optimizing capacitance and resistance through a matrix arrangement and dielectric layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If inter-digitated capacitor structure is used, then capacitance is improved, but resistance increases and matching deteriorates

Engineering Contradiction:
ImprovecapacitanceVSAvoidresistance and matching
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from a planar inter-digitated capacitor structure to a three-dimensional stacked structure. Multiple capacitor units are arranged vertically with conductive layers at different heights, utilizing the third dimension (vertical stacking) to increase capacitance without increasing planar footprint. This dimensional change also provides multiple electrical connection paths, reducing resistance and improving matching characteristics.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The capacitor structure is divided into multiple discrete capacitor units, each with its own conductive layers and dielectric regions. These segmented units are arranged in a matrix pattern with conductive grids and isolated islands, allowing independent optimization of each unit while collectively achieving low resistance through parallel connection paths.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If finger parts are extended to increase capacitance, then capacitance is improved, but resistance increases due to longer current paths

Engineering Contradiction:
ImprovecapacitanceVSAvoidresistance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

Instead of extending finger parts in the planar direction which increases resistance, the patent stacks capacitor units vertically. This utilizes the vertical dimension to increase capacitance while maintaining short current paths within each unit, thereby avoiding the resistance penalty associated with extended planar fingers.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Multiple capacitor units are merged into a single integrated structure where conductive layers from different units are interconnected. The conductive grids and islands from multiple units form a unified electrical network, providing multiple parallel current paths that reduce overall resistance while maintaining the increased capacitance from all units.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS7298001B1Three-dimensional capacitor structure
Publication Date: 2007.11.20 JMICRON
  • US7298001B1 patent drawing
  • US7298001B1 patent drawing
  • US7298001B1 patent drawing

AI summary

A three-dimensional capacitor structure has a first conductive layer, a second conductive layer disposed above the first conductive layer, and a plug layer disposed therebetween. The first conductive layer includes a plurality of grid units arranged in a matrix, where in odd rows of the matrix, a first conductive grid is located in each odd column, and a first circular hole is located in each even column. Additionally, a first conductive island is located within each first circular hole. The pattern of the second conductive grids, the second circular holes, and the second conductive island of the second conductive layer is mismatched with that of the first conductive layer. The plug layer has a plurality of plugs disposed in between each first conductive island and each second conductive grid, and in between each first conductive grid and each second conductive island.