3D Capacitor Structure With Trench Isolation
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Solution Overview
Problem
3D-capacitor structures with double layer stacks face challenges in achieving high capacitor density while minimizing equivalent serial resistance and preventing short-circuits between electrodes, particularly due to the limited conductivity and thickness of the second electrode layer.
Innovation Solution
A 3D-capacitor structure design featuring a substrate with a trench network and a double capacitor layer stack where additional substrate portions form closed-loop trench separations around contact-supporting pillars, isolating the third electrode and allowing contact pads to connect to the second electrode without causing short-circuits, thereby maintaining high capacitor density and low equivalent serial resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a double capacitor layer stack is used to increase capacitor density, then the capacitor density is improved, but the equivalent serial resistance increases due to the thin and limited conductivity of the second electrode layer
Solution Approach 1:
The patent divides the capacitor structure into multiple independent capacitor units arranged in parallel. Each unit has its own electrode layers and insulating layers, allowing the total capacitance to be increased without requiring a single thick second electrode layer, thus maintaining low equivalent serial resistance while achieving high capacitor density.
Solution Approach 2:
The patent transitions from a planar capacitor structure to a three-dimensional structure by stacking multiple capacitor layers vertically. This dimensional change allows increased capacitor density without increasing the area of individual electrode layers, thereby avoiding the need for thicker second electrode layers that would increase equivalent serial resistance.
2Reliability
If electrical contacts are provided to the second electrode to reduce equivalent serial resistance, then the equivalent serial resistance is improved, but short-circuits between the second and third electrodes may occur near the top edges of the trenches
Solution Approach 1:
The patent extracts or removes the third electrode layer specifically at the contact areas where electrical contacts are made to the second electrode. This creates isolated contact regions that allow direct access to the second electrode without the risk of short-circuiting to the third electrode, enabling low equivalent serial resistance while preventing harmful short-circuits.
Solution Approach 2:
The patent introduces an insulating layer that acts as an intermediary between the second and third electrodes in areas adjacent to contact regions. This intermediary structure prevents direct electrical contact between the second and third electrodes, eliminating short-circuit risks while allowing electrical contacts to be made to the second electrode for reducing equivalent serial resistance.
3Ease of manufacture
If the electrode layers are arranged parallel to the substrate top face to facilitate contact removal, then the ease of manufacture is improved, but the capacitor density decreases
Solution Approach 1:
The patent adopts a vertical stacking architecture where capacitor layers are arranged perpendicular to the substrate surface rather than parallel. This three-dimensional arrangement maximizes capacitor density within the available vertical space while maintaining planar contact areas at the top surface that are easy to manufacture and access for electrical contacts.
Data Source
Figure 1
Figure 1A
Figure 2~3
AI summary
A 3D-capacitor structure is based on a trench network which is etched from a top face (S100) of a substrate (100), and forms a regular array of separated pillars (10). The 3D-capacitor structure comprises a double capacitor layer stack which extends continuously on top faces of the pillars (10) at the substrate top face, on trench sidewalls and also on a trench bottom (S101). The trench network is modified locally for contacting a second electrode of the double capacitor layer stack while ensuring that no unwanted short-circuit may occur between said second electrode and a third electrode of said double capacitor layer stack. The invention provides an improved trade-off between high capacitor density and certainty of no unwanted short-circuit.