3D CCD Memory Architecture for Block-Addressable Storage Class Memory
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Solution Overview
Problem
The existing memory technologies, such as DRAM, PCM, MRAM, and NAND, fail to bridge the gap between low-cost storage memory and high-speed working memory due to scalability, power efficiency, or cycling capability limitations, necessitating a new class of memory like CCD-based block-addressable SCM.
Innovation Solution
A 3D integrated CCD memory array architecture with alternating gate and spacer layers, semiconductor-based channels, and charge storage capacitors, enabling high memory cell density, block-addressability, and efficient read/write schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional DRAM architecture is used, then byte-addressability is achieved, but scalability and cost-effectiveness deteriorate due to approaching scaling brick wall
Solution Approach 1:
The patent transitions from conventional 2D DRAM architecture to a 3D stacked architecture with multiple layers of memory cells vertically arranged. This dimensional change enables continued scalability by utilizing the third dimension (vertical stacking) to increase storage capacity without proportionally increasing the footprint area, thereby overcoming the scaling brick wall of conventional DRAM.
Solution Approach 2:
The memory array is divided into multiple independently addressable blocks, where each block can be selectively accessed and operated upon. This segmentation enables efficient block-addressable operations, allowing entire blocks to be read or written in parallel, thereby improving scalability and throughput while maintaining cost-effectiveness.
2Productivity
If phase change memory (PCM) is used, then scalability is improved, but power efficiency deteriorates
Solution Approach 1:
The patent replaces the thermal-based phase change mechanism of PCM with an electric field-based charge storage mechanism using CCD technology. This substitution eliminates the need for repeated heating and cooling cycles, thereby maintaining scalability while dramatically improving power efficiency by reducing energy consumption during write and refresh operations.
Solution Approach 2:
The invention changes the fundamental operating parameter from thermal state (in PCM) to electrical charge state (in CCD). By storing data as trapped charges in potential wells rather than phase states, the system achieves comparable scalability with significantly lower power consumption, as charge storage requires minimal energy compared to phase transitions.
3Use of energy by moving object
If magnetic random access memory (MRAM) is used, then power efficiency is improved, but cycling capability deteriorates
Solution Approach 1:
The patent replaces the magnetic tunnel junction switching mechanism of MRAM with a charge-based CCD storage mechanism. This substitution provides superior cycling capability because charge trapping and release in CCD potential wells can withstand billions of write cycles without degradation, whereas magnetic domain switching in MRAM suffers from gradual deterioration of magnetic properties over time.
4Reliability
If low-latency NAND memory is used, then cycling capability is improved, but power efficiency deteriorates
Solution Approach 1:
The patent implements a refresh mechanism that periodically restores charge in selected memory blocks only when necessary, rather than continuously refreshing all cells. This periodic action significantly reduces power consumption compared to continuous refresh schemes, while maintaining the high cycling capability inherent to NAND-based charge storage technology.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Achieves high memory cell densities, low power consumption, nearly unlimited cycling, and improved performance with reduced power consumption, while allowing block and sub-block addressing.
Implementation Method 1
a plurality of strings of charge storage capacitors operable as a plurality of CCD registers
Implementation Method 2
a layer stack including a plurality of gate layers and spacer layers, which are alternatingly arranged one on the other along a first direction
Data Source
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AI summary
The present disclosure relates to a three-dimensional (3D) integrated charge coupled device (CCD) block-addressable storage class memory (SCM). This 3D CCD memory comprises a layer stack including a plurality of gate layers and spacer layers, which are alternatingly arranged one on the other along a first direction. The memory further comprises a plurality of semiconductor-based channels extending in the stack, wherein the channels form, in combination with the gate layers and one or more dielectric layers, a plurality of strings of charge storage capacitors operable as a plurality of CCD registers. The memory includes a plurality of blocks, wherein each block comprises a plurality of sub-blocks, and wherein each sub-block comprises a set of the CCD registers. Each block and each sub-block of the block is individually selectable, in order to write information into at least one CCD register of the sub-block of the block.