3D CDAC Layout for Faster SAR ADCs With Lower Parasitics
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Solution Overview
Problem
The layout of capacitive digital-to-analog converters (CDACs) in successive approximation register analog-to-digital converters (SAR ADCs) occupies a large area, leading to increased parasitic capacitance and reduced operation speed.
Innovation Solution
A capacitive digital-to-analog converter (CDAC) with a three-dimensional layout is proposed, featuring a capacitive structure and a control logic circuit with switch groups. The capacitive structure is located in a third metal layer, and the control logic circuit is formed in lower metal layers, with vias providing connections, thereby reducing area occupation and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the CDAC uses a conventional two-dimensional layout, then the routing is simple, but the area occupied is large and parasitic capacitance increases
Solution Approach 1:
The patent transitions from a conventional two-dimensional layout to a three-dimensional layout by stacking metal layers vertically. The capacitive structure is placed in a third metal layer above the control logic circuit, which resides in lower metal layers. This vertical stacking reduces the horizontal area occupied by the CDAC while managing routing complexity through structured via connections between layers.
2Speed
If the CDAC occupies a large area, then the routing is simpler, but parasitic capacitance increases affecting operation speed
Solution Approach 1:
By moving the capacitive structure to a third metal layer above the control logic circuit, the patent reduces the horizontal area occupied by the CDAC. This vertical separation also reduces parasitic capacitance between routing lines and the capacitive structure, thereby improving operation speed while maintaining a compact footprint.
Solution Approach 2:
The patent introduces vias as intermediary elements to connect the control logic circuit in lower metal layers to the capacitive structure in the third metal layer. These vias provide controlled electrical connections while minimizing parasitic effects, enabling the separated vertical layout to function as a unified circuit.
3Area of stationary object
If the capacitive structure is placed in the same metal layer as the control logic circuit, then the routing is simpler, but the area occupied increases
Solution Approach 1:
The patent resolves the area-complexity tradeoff by placing the capacitive structure in a third metal layer vertically above the control logic circuit in lower metal layers. This vertical separation reduces horizontal area occupation while the added complexity is managed through systematic via connections that link the different layers.
Solution Approach 2:
The patent segments the CDAC into distinct vertical layers: the control logic circuit in lower metal layers and the capacitive structure in the third metal layer. This segmentation allows each component to be optimized independently while reducing overall area through vertical stacking, with vias providing the necessary inter-layer connections.
Data Source
AI summary
A capacitive digital-to-analog converter (CDAC) comprising a capacitive structure and a control logic circuit coupled to each other is provided. The control logic circuit comprises switch groups that each comprises first and second switch circuits. The first and second switch circuits each comprise first, second terminals, a first via and a control terminal. The first terminal is configured to receive a source voltage or a ground voltage through a first metal layer of the CDAC. The second terminal is configured to be coupled to the capacitive structure through the first via extending in a vertical direction. The control terminal is configured to receive one of a plurality of turn-on signals through a second metal layer of the CDAC. The capacitive structure is located at least in a third metal layer of the CDAC. The third metal layer is located above the first and second metal layers.