3D CDAC Layout With Shielding Layers for SAR ADC Area Reduction
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Solution Overview
Problem
The layout of existing capacitive digital-to-analog converters (CDACs) in successive approximation register analog-to-digital converters (SAR ADCs) occupies a large area, leading to increased circuit complexity and interference from routing signals, which affects the operation of capacitors.
Innovation Solution
A capacitive digital-to-analog converter (CDAC) with a three-dimensional layout is proposed, featuring a capacitive structure and a control logic circuit. The capacitive structure is located in a second metal layer, while the control logic circuit and shielding layers are in different metal layers, reducing the overall area and minimizing signal interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the CDAC uses a conventional two-dimensional layout, then the routing is simple, but the area occupied is large and routing signals interfere with capacitor operation
Solution Approach 1:
The patent transitions from a conventional two-dimensional layout to a three-dimensional stacked architecture where capacitive structures are placed in upper metal layers (M5-M7) above the control logic circuit in lower layers (M1-M4). This vertical stacking reduces the planar area footprint while managing routing complexity through multiple layers and shielding structures.
Solution Approach 2:
The patent embeds shielding layers (M1, M2) within the stacked structure to enclose and protect the capacitive structures in upper layers from external interference. The control logic circuit in lower layers is nested within the vertical stack, with capacitive elements positioned above it, creating a compact nested arrangement that reduces overall area.
2Reliability
If the CDAC occupies a large area, then routing can be simplified, but the SAR ADC total area increases and capacitor operation is affected
Solution Approach 1:
The patent extracts the capacitive structures from the planar domain and relocates them to upper metal layers (M5-M7), separating them physically from the control logic circuit in lower layers. This extraction reduces planar area occupation while shielding layers are introduced to protect the extracted capacitive elements from interference, maintaining operational reliability.
Solution Approach 2:
Shielding layers (M1, M2) are introduced as intermediary structures between the control logic circuit and external environment, and between different functional blocks. These shielding layers act as mediators that block interference from routing signals and external sources, protecting the capacitive structures while enabling compact stacking.
3Area of stationary object
If routing signals are placed close to capacitive structures, then area is reduced, but signal interference increases
Solution Approach 1:
The patent vertically separates routing signals in lower metal layers (M1-M4) from capacitive structures in upper metal layers (M5-M7). This dimensional separation allows area reduction through stacking while minimizing capacitive coupling and interference between routing signals and capacitive elements through layer isolation.
Solution Approach 2:
Grounded shielding layers (M1, M2) are positioned as intermediaries between the control logic circuit with routing signals and the capacitive structures. These shielding layers form capacitive dividers that redirect interference signals to ground, preventing them from reaching the sensitive capacitive elements while maintaining compact vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The three-dimensional layout of the CDAC reduces the total area of the SAR ADC, alleviates the effect of routing signals on capacitive structures, and improves the performance of both the CDAC and SAR ADC.
Implementation Method 1
A first terminal of the first switch circuit is configured to receive the positive reference voltage through a first shielding layer of the CDAC. The first terminal of the second switch circuit is configured to receive the negative reference voltage through a second shielding layer of the CDAC.
Data Source
AI summary
A capacitive digital-to-analog converter (CDAC) comprising a capacitive structure and a control logic circuit coupled to each other is provided. Two terminals of the capacitive structure respectively receive positive and negative reference voltages. The control logic circuit comprises switch groups that each comprises first and second switch circuits. The first and second switch circuits each comprise first, second terminals and a control terminal. The first terminals of the first and second switch circuits respectively receive positive and negative reference voltages, through first and second shielding layers of the CDAC respectively. The second terminal is coupled to the capacitive structure. The control terminal receives one of turn-on signals through a first metal layer of the CDAC. The capacitive structure is located at least in a second metal layer of the CDAC. The first and second shielding layers are above the first metal layer and below the second metal layer.