3D Semiconductor Cell Layout With Split Gates and Conductive Plates
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration and improved electrical characteristics due to the scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs), leading to deteriorated operating characteristics and increased area requirements.
Innovation Solution
A three-dimensional semiconductor device design featuring vertically stacked transistors with a backside metal layer, channel patterns, gate electrodes, and conductive plates in a separation insulating pattern, allowing for reduced cell height and improved integration through symmetric conductive plate arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET sizes are scaled down to achieve higher integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar two-dimensional transistor布局 to three-dimensional vertically stacked transistor structures. Multiple channel patterns (first lower channel patterns, first upper channel patterns, second lower channel patterns, second upper channel patterns) are stacked vertically to increase device density while maintaining acceptable operating characteristics through controlled channel dimensions.
Solution Approach 2:
The transistor structure is divided into multiple segments: lower and upper channel patterns, first and second gate electrodes, and associated conductive plates. This segmentation allows independent optimization of each segment's dimensions and properties to maintain performance while achieving high integration.
2Area of stationary object
If transistor dimensions are reduced for higher integration, then area decreases, but electrical characteristics deteriorate
Solution Approach 1:
The invention utilizes vertical stacking to reduce the planar footprint of the transistor cell. By arranging channel patterns and gate electrodes in three dimensions rather than two dimensions, the cell area is significantly reduced while the electrical characteristics are maintained through proper control of vertical channel dimensions and gate overlap.
Solution Approach 2:
The structure employs nested arrangements where upper channel patterns are positioned above lower channel patterns, and gate electrodes surround or overlap channel patterns in multiple dimensions. This nesting maximizes space utilization and reduces overall cell area while maintaining functional integrity.
3Productivity
If vertically stacked transistor structure is implemented, then integration is improved, but electrical interference increases
Solution Approach 1:
Separation insulating patterns are introduced as intermediary layers between adjacent gate electrodes and between different transistor components. These insulating patterns electrically isolate neighboring structures, preventing harmful electrical interference and crosstalk while allowing the vertically stacked configuration to achieve high integration.
4Productivity
If complex three-dimensional structure is created, then integration is enhanced, but manufacturing complexity increases
Solution Approach 1:
The complex three-dimensional structure is broken down into manageable segments that can be formed through sequential processing steps. Each segment (channel patterns, gate electrodes, conductive plates, insulating layers) is formed independently and then assembled into the final structure, making manufacturing more controllable despite the overall complexity.
Solution Approach 2:
Certain structures are formed in advance as preliminary steps before final assembly. For example, separation insulating patterns and conductive plates are prepared beforehand, and channel patterns are formed with predetermined dimensions and positions to facilitate subsequent gate electrode formation and reduce overall manufacturing complexity.
Data Source
AI summary
A three-dimensional semiconductor device includes a backside metal layer, a lower channel pattern and an upper channel pattern sequentially provided on the backside metal layer, a gate electrode crossing the lower and upper channel patterns in a first direction, and including a first gate electrode and a second gate electrode adjacent to each other in the first direction, a separation insulating pattern between the first and second gate electrodes, and a conductive plate extending in the separation insulating pattern in each of a second direction intersecting the first direction and a third direction perpendicular to the first direction, wherein the conductive plate includes a first conductive plate and a second conductive plate adjacent to each other in the first direction in the separation insulating pattern.