Precision-Aligned 3D CFET Architecture With 2D Channel Materials
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Solution Overview
Problem
Current semiconductor manufacturing techniques are limited by two-dimensional (2D) fabrication methods, which restrict the complexity and integration of semiconductor devices, particularly in achieving three-dimensional (3D) stacked structures with aligned NMOS and PMOS devices for CFETs.
Innovation Solution
The proposed method involves forming a low-process-temperature 3D stack with aligned NMOS and PMOS devices using the gate electrode as the initial device geometry, allowing for a precision 3D stack of channel and gate regions. This method does not require epitaxial silicon on the base substrate, enabling flexibility in base materials and allowing transistors to be integrated at any stage of the process flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If 2D fabrication techniques are used to manufacture transistors on a single active device plane, then the manufacturing process is simple and well-established, but the device complexity and integration density are limited
Solution Approach 1:
The patent transitions from 2D planar fabrication to 3D vertical stacking by forming transistor structures in multiple layers. The gate electrode is formed as an initial 3D geometry, and channel regions are deposited conformally around it, creating vertically stacked NMOS and PMOS transistors that occupy three-dimensional space rather than being confined to a single plane. This dimensional change enables higher device complexity and integration density.
Solution Approach 2:
The patent implements nested structures where channel regions are conformally deposited around gate electrodes, and multiple transistor structures are stacked vertically within a compact footprint. The 3D stack configuration allows transistor structures to be nested in the vertical dimension, achieving higher integration without proportionally increasing the lateral manufacturing complexity.
2Adaptability or versatility
If epitaxial silicon is required on the base substrate, then the device performance is optimized, but the base material selection is restricted and process temperature must be high
Solution Approach 1:
The patent changes the process temperature parameter from high-temperature epitaxial growth to low-temperature conformal deposition. By using atomic layer deposition (ALD) or chemical vapor deposition (CVD) at lower temperatures, the method enables formation of channel and gate dielectric regions without requiring epitaxial silicon, thus expanding base material options to include silicon-germanium, silicon-carbide, and other advanced substrates.
Solution Approach 2:
The patent replaces the mechanical/chemical process of epitaxial growth with conformal deposition techniques. Instead of growing silicon layers through high-temperature epitaxy, the method uses vapor-phase deposition to form thin film layers conformally on the 3D gate electrode structure, substituting one manufacturing mechanism for another that enables lower temperatures and greater material versatility.
3Productivity
If transistors are formed early in the process flow, then the device structure is established, but the number of process steps increases and manufacturing efficiency decreases
Solution Approach 1:
The patent performs preliminary action by forming the gate electrode structure first as the initial geometry, then depositing channel and gate dielectric regions conformally around it. This preliminary gate formation enables subsequent steps to be performed in a streamlined sequence, reducing the total number of process steps compared to traditional approaches where transistors are formed early and require numerous subsequent alignment and fabrication steps.
Data Source
AI summary
A method for manufacturing a semiconductor device is described. The method includes forming a first complementary field effect transistor. The first complementary field effect transistor has a first transistor of a first conductivity type, and a second transistor of a second conductivity above the first transistor. The first transistor includes a first gate electrode, a first channel above the first gate electrode, and first source and drain contacts above the first channel layer. The second transistor includes a second gate electrode, a second channel, and second source and drain contacts. The second channel is disposed between the second source and drain contacts and the second gate electrode. At least one of the first channel or the second channel includes a two-dimensional semiconductor material or an oxide semiconductor.