3D CFET Routing Layout With Dual-Sided Metal Access
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Solution Overview
Problem
Conventional complementary-FET (CFET) layouts face challenges in design density due to limited routing resources, as all routing is confined to the front side of the device, leading to reduced efficiency and increased complexity in integrated circuits.
Innovation Solution
The implementation of a three-dimensional (3D) CFET design with metal lines on both sides of the gate structure, enabling routing from both the front and back sides, and a cell swap method to optimize I/O pin connections and alleviate routing congestion, thereby enhancing design density without losing routing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If all routing resources are confined to the front side of the CFET device, then the device structure remains simple and manageable, but the design density is reduced and routing efficiency is impacted
Solution Approach 1:
The patent applies dimensionality change by transitioning from two-dimensional front-side-only routing to three-dimensional dual-sided routing. Metal lines are formed both above and below the gate structure, utilizing the vertical dimension and back side of the device to create additional routing layers. This allows signals to be routed from both front and back sides, effectively doubling the available routing resources and improving design density without significantly increasing structural complexity.
2Productivity
If metal lines are formed both above and below the gate structure for dual-sided routing, then routing resources are enhanced and design density is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the routing function into separate front-side and back-side metal line formations. The manufacturing process is segmented into distinct stages: forming first metal lines above the gate structure, then forming second metal lines below the gate structure. This segmentation allows each routing layer to be manufactured independently using standard semiconductor fabrication techniques, making the complex dual-sided routing process manageable and scalable.
3Ease of manufacture
If conventional CFET layouts with front-side-only routing are used, then the manufacturing process remains straightforward, but routing congestion increases and design efficiency decreases
Solution Approach 1:
The patent resolves routing congestion by adding the third dimension to routing architecture. Instead of confining all metal lines to the front side, the invention forms metal lines both above and below the gate structure, creating multiple routing planes. This dimensional expansion distributes routing traffic across more pathways, reducing congestion and improving signal routing efficiency while maintaining compatibility with existing manufacturing processes.
Data Source
AI summary
Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.