3D CFET Inter-Level Handshake to Reduce Wiring Congestion
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Solution Overview
Problem
Conventional two-dimensional semiconductor fabrication faces challenges in scaling as it reaches single-digit nanometer nodes, with increased transistor density leading to wiring congestion and reduced footprint area, making it difficult to connect transistors efficiently in three-dimensional circuits.
Innovation Solution
The solution involves a semiconductor device with a vertical stack of complementary field-effect transistors (CFETs) where inter-level connections are formed with a lateral offset, allowing for direct connections between source/drain regions and gates across different device planes, reducing wiring congestion through a conductive metal wiring structure and self-aligned contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional two-dimensional semiconductor fabrication is used to increase transistor density, then transistor density is improved, but wiring congestion increases and footprint area is reduced
Solution Approach 1:
The patent transitions from conventional two-dimensional circuit layout to three-dimensional vertical stacking of transistors. Multiple device planes are stacked vertically with inter-level connections providing lateral offsets between channels of different planes, enabling direct vertical connections between source/drain regions and gates across planes. This dimensional change increases transistor density while reducing wiring congestion by utilizing vertical space rather than lateral routing.
2Quantity of substance
If conventional two-dimensional semiconductor fabrication is used to increase transistor density, then transistor density is improved, but footprint area is reduced
Solution Approach 1:
The patent employs vertical stacking of multiple device planes to increase transistor density without proportionally increasing footprint area. By stacking transistors vertically and using inter-level connections with lateral offsets, the design utilizes the third dimension (vertical space) to accommodate more transistors within the same lateral footprint, effectively decoupling density from area expansion.
3Quantity of substance
If three-dimensional transistor stacking is implemented, then transistor density is improved, but inter-level connections become more complex
Solution Approach 1:
The patent forms inter-level connections with lateral offsets between channels of different device planes during the fabrication process. This preliminary positioning of connection structures enables direct vertical connections between source/drain regions and gates across planes, simplifying the overall inter-level connection architecture by pre-establishing alignment pathways rather than requiring complex post-fabrication routing.
Data Source
AI summary
A semiconductor device includes a first device plane over a substrate. The first device plane includes a first transistor device having a first source/drain (S/D) region formed in an S/D channel. A second device plane is formed over the first device plane. The second device plane includes a second transistor device having a second gate formed in a gate channel which is adjacent to the S/D channel. A first inter-level connection is formed from the first S/D region of the first transistor device to the second gate of the second transistor device. The first inter-level connection includes a lateral offset from the S/D channel to the gate channel.