3D CFET ROM Cell Layout for Low-Power High-Density Memory
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Solution Overview
Problem
The increasing off-current due to excessive scaling in transistors leads to significant power consumption in semiconductor storage devices, necessitating the development of more efficient three-dimensional transistor structures.
Innovation Solution
A layout structure for a mask ROM using complementary FET (CFET) devices, where three-dimensional transistors are stacked vertically, with channel portions overlapping each other, and local interconnects connecting sources and drains to bit lines and ground power supply lines, allowing for data storage based on connection states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are scaled down to improve integration degree and operating speed, then integration degree and operating speed are improved, but off current increases significantly leading to higher power consumption
Solution Approach 1:
The patent transitions from conventional planar transistors to three-dimensional vertically stacked CFET structures. By stacking p-type and n-type FETs vertically, the invention achieves higher integration density without further scaling the gate length, thereby avoiding the off-current increase associated with excessive scaling. This dimensional transition resolves the contradiction between integration degree and power consumption.
2Power
If transistors are scaled down to reduce operating voltage, then operating voltage is reduced, but off current increases significantly leading to higher power consumption
Solution Approach 1:
The vertically stacked CFET structure enables reduced operating voltage through improved gate control over the channel, while avoiding further gate length scaling. The three-dimensional configuration provides better electrostatic control that suppresses off-current even at lower voltages, resolving the contradiction between operating voltage reduction and power consumption.
3Ease of manufacture
If conventional planar transistors are used in mask ROM, then manufacturing is simple, but area efficiency is limited
Solution Approach 1:
The patent employs vertically stacked CFETs where p-type and n-type transistors are stacked in the depth direction with overlapping channel portions. This three-dimensional arrangement reduces the planar footprint of each memory cell while maintaining manufacturability through standard semiconductor fabrication processes adapted for vertical structures.
Solution Approach 2:
Adjacent transistors share common source and drain regions, and the vertically stacked configuration merges the spatial occupation of multiple transistors into a single vertical column. This merging approach reduces the overall area required for memory cells while keeping the manufacturing process relatively straightforward.
4Productivity
If three-dimensional vertically stacked CFETs are used, then integration density is improved, but device structure becomes more complex
Solution Approach 1:
The invention adopts vertically stacked CFETs with p-type and n-type transistors arranged in the depth direction. This three-dimensional structure doubles the transistor density per unit area compared to planar configurations, achieving higher integration density while using established fabrication techniques modified for vertical stacking.
Data Source
AI summary
A ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored depending on whether first and second local interconnects connected to the nodes of the first transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line. Second data is stored depending on whether third and fourth local interconnects connected to the nodes of the second transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line.