3D Semiconductor Channel Structure for Higher Driving Current
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Solution Overview
Problem
Conventional planar MOS transistors face challenges in scaling down, leading to the development of stereoscopic and non-planar transistor technologies like FinFETs and gate-all-around nanowire FETs, but there is a need to further enhance electrical performance through structural design and process improvements.
Innovation Solution
A manufacturing method for semiconductor devices that incorporates a semiconductor channel structure with both horizontal and vertical portions, where the vertical portion is connected to the horizontal portions, increasing the surface area and providing a higher carrier mobility lattice plane, thereby enhancing electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar MOS transistor structure is used, then manufacturing process is simple, but device scaling down is difficult and electrical performance is limited
Solution Approach 1:
The patent transitions from a conventional planar (2D) channel structure to a three-dimensional channel structure comprising stacked horizontal portions and vertical portions. This dimensional change increases the effective channel surface area available for carrier transport while maintaining a compact footprint, thereby improving electrical performance without complicating the fundamental manufacturing approach
2Productivity
If transistor size is reduced for miniaturization, then integration density increases, but electrical performance deteriorates
Solution Approach 1:
By stacking multiple horizontal portions vertically and adding vertical portions, the invention creates a multi-dimensional channel structure that increases the effective channel area within a reduced planar footprint. This allows higher integration density while maintaining or improving electrical performance through increased carrier transport pathways
Solution Approach 2:
The channel structure employs a nested configuration where vertical portions connect and extend from horizontal portions, creating a hierarchical arrangement. This nested structure maximizes the use of available space by nesting channel segments at different vertical levels, achieving high integration density without sacrificing electrical performance
3Reliability
If channel surface area is increased to improve electrical performance, then device size increases, but integration density decreases
Solution Approach 1:
The patent resolves this contradiction by extending the channel structure into the vertical dimension through stacked horizontal portions and vertical connectors. This allows the effective channel surface area to be increased while the planar footprint remains compact, as the additional channel area is achieved through vertical stacking rather than lateral expansion
Data Source
AI summary
A manufacturing method of a semiconductor device includes the following steps. A first transistor is formed on a substrate. The first transistor includes a first semiconductor channel structure and two first source/drain structures. The first semiconductor channel structure includes first horizontal portions and a first vertical portion. The first horizontal portions are stacked in a vertical direction and separated from one another. Each of the first horizontal portions is elongated in a horizontal direction. The first vertical portion is elongated in the vertical direction and connected with the first horizontal portions. The two first source/drain structures are disposed at two opposite sides of each of the first horizontal portions in the horizontal direction respectively. The two first source/drain structures are connected with the first horizontal portions. A top surface of the first vertical portion in and a top surface of one of the first horizontal portions are coplanar.