3D Channel Semiconductor Devices With Dummy Gate Trench Segmentation
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Solution Overview
Problem
Current semiconductor devices with 3D channels face challenges in achieving optimal integration density and suppressing short channel effects, as existing techniques do not effectively manage gate lengths and channel region potentials.
Innovation Solution
The semiconductor device design includes a substrate with aligned fins, trenches, and field insulating films, where dummy gates are strategically placed on these films to control channel regions, allowing for varied trench depths and insulating film heights to manage gate lengths and channel potentials effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple gates are formed on surfaces of the silicon body to define 3D channel regions, then integration density is increased and short channel effects are suppressed, but manufacturing complexity increases due to varied trench depths and insulating film heights
Solution Approach 1:
The device structure is segmented into multiple fins (first to fourth fins) with trenches between them, allowing independent formation of field insulating films and dummy gates in each trench. This segmentation enables the complex 3D channel structure to be built through repeated, standardized processing steps rather than a single complex operation.
Solution Approach 2:
Field insulating films are formed in trenches between fins before the active gates are created. Dummy gates are also preliminarily formed on these field insulating films. These preliminary structures prepare the device for subsequent gate formation while establishing the 3D channel regions, simplifying the overall manufacturing sequence.
2Productivity
If gate length is reduced to scale down the device, then integration density increases, but short channel effects worsen due to inadequate current control
Solution Approach 1:
The invention transitions from planar gate structures to three-dimensional channel regions formed between multiple fins. The 3D channel regions extend vertically between the fins, providing enhanced gate control over the channel without requiring increased gate length. This dimensional change allows scaling while maintaining current control capability.
Solution Approach 2:
The device structure provides different qualities in different regions: active gates are formed on specific fins to control specific channel regions, while dummy gates are formed on field insulating films in trenches to provide local control and suppression of short channel effects. This localized quality differentiation enables effective current control in scaled devices.
3Reliability
If dummy gates are formed on field insulating films with varied heights, then channel region potentials are stabilized, but manufacturing precision requirements increase
Solution Approach 1:
Different trenches between fins are allowed to have different depths and field insulating film heights based on local requirements. The first and second trenches may have different depths, and the third and fourth trenches may have different depths. This local quality approach stabilizes channel potentials by adapting the field insulating film structure to specific device regions rather than requiring uniform precision throughout.
Solution Approach 2:
The device is divided into multiple independent trench regions, each with its own field insulating film and dummy gate. This segmentation allows each trench to be formed and filled independently, enabling varied depths and heights in different locations without compromising the overall device performance or requiring stringent uniformity across all trenches.
Data Source
AI summary
A semiconductor device includes a substrate including first to third fins aligned in a first direction, a first trench arranged between the first fin and the second fin, and a second trench arranged between the second fin and the third fin. The semiconductor device further includes a first field insulating film arranged in the first trench, a second field insulating film formed in the second trench, a first dummy gate arranged on the first field insulating film and a second dummy gate at least partly arranged on the second field insulating film. A lower surface of the second field insulating film is arranged to be lower than a lower surface of the first field insulating film.