3D Memory Channel Isolation for Stable Contact Pad Formation
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Solution Overview
Problem
The integration limits of two-dimensional nonvolatile memory devices have been reached, necessitating the development of three-dimensional structures, which require improved operational reliability and stability.
Innovation Solution
A semiconductor device with a gate structure comprising alternately stacked conductive and insulating layers, channel structures, and cutting structures that isolate and enhance contact pads, allowing for increased memory cell density and improved manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two-dimensional nonvolatile memory devices are used, then manufacturing is simpler, but integration density reaches its limit
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple conductive layers (first conductive layer, second conductive layer, third conductive layer) are stacked vertically to increase storage capacity per unit area, thereby overcoming the integration density limit of two-dimensional devices while maintaining manufacturability through systematic layering
2Productivity
If three-dimensional stacked structure is implemented, then memory cell density increases, but operational reliability decreases
Solution Approach 1:
The patent divides the three-dimensional stacked structure into multiple independent functional layers (first conductive layer, second conductive layer, third conductive layer, interlayer insulating layers) that can be manufactured and tested separately. This segmentation allows for quality control at each layer while achieving high overall density, thereby maintaining reliability despite increased complexity
Solution Approach 2:
The patent forms the complete multi-layer stacked structure with all conductive layers and insulating layers before final processing steps. This preliminary formation ensures proper alignment and integration of all components, reducing defects and improving operational reliability of the high-density three-dimensional structure
3Manufacturing precision
If contact pad critical dimension is reduced, then manufacturing precision improves, but contact reliability worsens
Solution Approach 1:
The patent implements a nested structure where the contact pad is positioned within an opening formed through the interlayer insulating layer, which itself is part of the larger stacked structure. This nested arrangement allows the contact pad to be precisely defined by the opening dimensions while maintaining adequate contact area for reliability, effectively decoupling manufacturing precision requirements from contact reliability requirements
Data Source
AI summary
A semiconductor device, and a method of manufacturing the semiconductor device, includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; a channel structure including a first channel structure and a second channel structure aligned in a first direction, and the channel structure penetrating the gate structure, a first cutting structure extending in a second direction, the first cutting structure disposed between the first channel structure and the second channel structure; a contact pad including a first contact pad in contact with an upper surface of the first channel structure, and a second contact pad in contact with an upper surface of the second channel structure; a second cutting structure in contact with an upper surface of the first cutting structure and disposed between the first contact pad and the second contact pad, wherein the first contact pad has a critical dimension greater than a critical dimension of the upper surface of the first channel structure.