3D Channel Passivation Structure for Low-Leakage Memory Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in microelectronic devices is to maintain memory density while reducing the size of transistors, which leads to increased off current due to traps and defects in the channel regions, resulting in reduced charge retention and frequent memory bit refreshes.
Innovation Solution
The implementation of a microelectronic device with a vertically oriented channel material extending into conductive lines and a passivation material between channel material portions, forming a bilayer structure that reduces off current and stress-induced threshold voltage degradation by increasing contact area and passivating deep donor states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of gate dielectric material is decreased to increase memory density, then off current initially decreases, but off current begins to increase due to band-to-band tunneling and low band gap
Solution Approach 1:
The patent changes the material parameter of the channel region from conventional silicon to a high band gap semiconductor material. This parameter change increases the band gap energy, which suppresses band-to-band tunneling and reduces off current even when the gate dielectric thickness is decreased to increase memory density.
Solution Approach 2:
The patent employs a composite structure combining a high band gap semiconductor material channel region with a gate dielectric material. This composite material system leverages the high band gap property to prevent tunneling while maintaining the insulating function of the gate dielectric, resolving the contradiction between thinning the dielectric for density and maintaining low off current.
2Quantity of substance
If the size of channel region is decreased to increase memory density, then the contact area between channel region and conductive contacts is reduced, resulting in increased resistance and decreased on-state current
Solution Approach 1:
The patent changes the electrical parameter of the channel material to a high band gap semiconductor, which enables better interface properties and reduced contact resistance. This material parameter change compensates for the reduced contact area, maintaining on-state current while achieving higher memory density through smaller channel dimensions.
3Reliability
If conventional semiconductor materials are used in channel regions, then traps and defects increase off current, but switching to alternative materials may affect manufacturing process compatibility
Solution Approach 1:
The patent changes the fundamental material parameter from silicon to a high band gap semiconductor material that can be deposited using existing semiconductor fabrication techniques such as chemical vapor deposition or atomic layer deposition. This maintains ease of manufacture while achieving the reliability improvement of reduced off current through the material's inherent high band gap property.
Data Source
AI summary
A microelectronic device comprises a conductive line and a transistor adjacent to the conductive line. The transistor comprises a channel material extending into the conductive line, the channel material contacting the conductive line in three dimensions, a dielectric material adjacent to the channel material, a conductive material adjacent to the dielectric material, and a passivation material adjacent to the channel material. The microelectronic device further comprises a conductive contact adjacent to the channel material, the conductive contact including a portion extending between opposing portions of the channel material. Related microelectronic devices, electronic devices, and related methods are also disclosed.