3D Channel Contact and Passivation for Scaled Transistors
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Solution Overview
Problem
The challenge in microelectronic devices is to maintain performance while scaling down transistor size, as reduced gate dielectric thickness leads to increased off current due to band-to-band tunneling and reduced contact area between the channel region and conductive contacts, resulting in decreased on-state current and transistor speed.
Innovation Solution
The solution involves forming a microelectronic device with a transistor that includes a vertically oriented channel region with a channel material extending into a conductive line and a passivation material located between portions of the channel material. This configuration increases the contact area between the channel material and the conductive line and contact, reducing electrical resistance and enhancing transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of the gate dielectric material is decreased to increase memory density, then the off current initially decreases, but the off current begins to undesirably increase due to band-to-band tunneling
Solution Approach 1:
The patent changes the material parameter of the channel region from conventional semiconductor materials (silicon, polysilicon) to a high band gap semiconductor material. This parameter change increases the band gap energy, which suppresses band-to-band tunneling effects even when the gate dielectric thickness is reduced, thereby maintaining low off current while enabling higher memory density.
Solution Approach 2:
The patent employs a composite structure consisting of a gate dielectric layer combined with a high band gap semiconductor channel material. This composite material system leverages the high band gap property of the semiconductor material to counteract the tunneling effects introduced by thin gate dielectric, resolving the contradiction between density and reliability.
2Quantity of substance
If the size of the channel region is decreased to increase memory density, then the contact area between the channel region and conductive contacts is reduced, resulting in increased resistance and decreased on-state current
Solution Approach 1:
The patent changes the electrical parameter of the channel material to a high band gap semiconductor, which enables better control of carrier transport properties. This allows for optimized contact interfaces and reduced contact resistance even in scaled-down devices, maintaining high on-state current despite reduced contact area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased contact area between the channel material and the conductive materials reduces contact resistance, leading to improved on-state current and operating speed of the transistor, while the passivation material reduces off current by passivating deep donor states and defects in the channel material.
Implementation Method 1
the passivation material reduces off current by passivating deep donor states and defects in the channel material
Data Source
AI summary
A microelectronic device comprises a conductive line and a transistor adjacent to the conductive line. The transistor comprises a channel material extending into the conductive line, the channel material contacting the conductive line in three dimensions, a dielectric material adjacent to the channel material, a conductive material adjacent to the dielectric material, and a passivation material adjacent to the channel material. The microelectronic device further comprises a conductive contact adjacent to the channel material, the conductive contact including a portion extending between opposing portions of the channel material. Related microelectronic devices, electronic devices, and related methods are also disclosed.