3D Channel Layer Structure for Scaled Semiconductor Reliability
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving improved electrical characteristics and reliability due to limitations in transistor structure design, particularly in scaling down sizes while maintaining high operating speed and accuracy.
Innovation Solution
A semiconductor device with a three-dimensional channel structure is developed, featuring a fin-type active region, multiple channel layers with varying widths, and a gate electrode that surrounds these layers, along with a gate insulating film and source/drain regions, which are fabricated using a method involving alternating semiconductor layers, etching, silicon epitaxial liner formation, and annealing processes to enhance channel layer width and shape for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of semiconductor devices is scaled down, then the density of integrated circuit devices is increased, but the electrical characteristics and reliability deteriorate
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional FinFET structures, extending the channel in the vertical dimension. This dimensional change increases the effective channel area and carrier transport capacity without increasing the planar footprint, thereby improving device density while maintaining electrical characteristics and reliability through enhanced gate control and larger channel volume.
2Speed
If the transistor structure is optimized for high operating speed, then the operating speed is improved, but the device complexity increases
Solution Approach 1:
The channel is segmented into multiple discrete layers (first channel layer, second channel layer, third channel layer) separated by insulating films. This segmentation enables independent optimization of each layer's electrical characteristics, improves gate control through reduced channel thickness, and enhances operating speed while managing complexity through modular layer design.
Solution Approach 2:
The patent implements nested channel layers where the second channel layer is positioned between the first and third channel layers, with each layer nested within the vertical structure. This nested configuration increases the effective channel area and carrier transport capacity for higher operating speed, while the compact vertical arrangement manages device complexity by utilizing the third dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design enhances direct current performance and reliability by increasing the volume of the channel region through optimized channel layer widths and shapes, leading to improved electrical characteristics.
Implementation Method 1
forming a silicon epitaxial liner on a surface of the fin-shaped structure
Implementation Method 2
applying an annealing process to the gap-fill insulating film
Data Source
AI summary
A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.