3D Semiconductor Channel Structure With Slit-Linked Source Junction
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Solution Overview
Problem
Current semiconductor devices with three-dimensional stacked structures face challenges in improving driving reliability due to limitations in the operational reliability of gate stack structures and the integration density of memory cells.
Innovation Solution
The semiconductor device incorporates a well structure with channel pillars and a gate stack structure, featuring a slit and a select channel pattern that extends into the slit, along with a source junction formed in the semiconductor pattern, to enhance electrical connections and reliability. The manufacturing method involves forming a sacrificial group, stack structure, and slit to create a horizontal space for the semiconductor pattern and source junction, improving the integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a three-dimensional stacked structure with gate stack structures is used to increase integration density, then the integration density of memory cells is improved, but the driving reliability deteriorates due to limitations in operational reliability
Solution Approach 1:
The semiconductor device divides the channel region into multiple segments by introducing select channel patterns between the well structure and gate stack structures. This segmentation allows independent control of different channel regions, improving reliability while maintaining high integration density through the three-dimensional stacked architecture.
Solution Approach 2:
Select channel patterns are introduced as intermediary structures between the well structure and gate stack structures. These intermediary select channel patterns provide additional control points and improve current flow management, thereby enhancing driving reliability without compromising the integration density achieved through stacking.
2Productivity
If gate stack structures are stacked on each other for high integration density, then integration density is improved, but operational reliability deteriorates
Solution Approach 1:
The channel region is segmented into multiple independent regions by introducing select channel patterns at different levels. This segmentation allows each stacked gate structure to control its own channel region independently, improving operational reliability while maintaining the high integration density benefits of the three-dimensional stacked configuration.
Solution Approach 2:
The invention transitions from a two-dimensional planar structure to a three-dimensional stacked structure with select channel patterns extending in the vertical dimension. This dimensional change enables independent control of multiple channel regions at different heights, improving operational reliability while achieving high integration density through vertical stacking.
3Reliability
If a slit and select channel pattern are introduced to improve current flow paths, then driving reliability is improved, but device complexity increases
Solution Approach 1:
The select channel patterns are merged with the existing well structure and gate stack structures to form an integrated three-dimensional architecture. This merging approach improves current flow paths and driving reliability while minimizing additional complexity by combining multiple functions into a unified structure rather than adding separate components.
Solution Approach 2:
The invention resolves the complexity issue by transitioning to three-dimensional stacking where select channel patterns extend vertically between the well structure and gate stack structures. This dimensional change allows improved current flow control without requiring complex lateral routing, as the select channel patterns naturally follow the vertical stacking architecture.
Data Source
AI summary
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well structure, a first channel pillar and a second channel pillar extending from an inside of the well structure in an upward direction, a semiconductor pattern coupled between the first channel pillar and the second channel pillar and having a gap disposed in a central region of the semiconductor pattern, and a source junction formed in the semiconductor pattern.