3D Semiconductor Channel Stack With Ferroelectric Interface Stabilization
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Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOSFETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved reliability in three-dimensional semiconductor devices.
Innovation Solution
A three-dimensional semiconductor device is designed with a first and second active region stacked on a substrate, featuring a first and second channel pattern connected by source/drain patterns, a gate electrode, and ferroelectric patterns interposed between the substrate and channel patterns, along with a gate electrode structure that three-dimensionally surrounds the channel patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFETs are scaled down to meet increasing demand for small pattern size, then device density and integration are improved, but operational properties and reliability deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar MOSFET structures to three-dimensional vertically-stacked channel patterns. Multiple channel patterns are stacked in the vertical direction, allowing increased device density without further lateral scaling. This dimensional change enables continued miniaturization while maintaining operational properties by preserving adequate channel dimensions in the lateral plane.
Solution Approach 2:
The patent introduces ferroelectric patterns as composite material structures between the substrate and channel patterns. These ferroelectric materials provide enhanced electrical characteristics and interface stability, improving reliability in the scaled-down three-dimensional structure. The composite structure combines semiconductor channel materials with ferroelectric materials to achieve both high density and operational stability.
2Productivity
If three-dimensional stacked structure is implemented to improve device density, then integration is enhanced, but interfacial property deterioration occurs
Solution Approach 1:
The patent introduces ferroelectric patterns as intermediary layers between the substrate and the vertically-stacked channel patterns. These intermediary ferroelectric structures serve as buffer zones that maintain stable electrical interfaces, preventing direct contact between potentially incompatible materials. This mediator approach preserves interfacial properties while enabling the three-dimensional stacked configuration for higher device density.
Solution Approach 2:
The patent utilizes ferroelectric materials with specific electrical parameters (high dielectric constant, stable polarization) to change the electrical characteristics at the substrate-channel interfaces. By selecting materials with optimized parameters, the patent maintains stable interfacial properties despite the increased complexity of the three-dimensional stacked structure, preventing interfacial degradation.
3Reliability
If ferroelectric patterns are introduced to improve electrical characteristics, then sub-threshold swing and operation voltage are enhanced, but device complexity increases
Solution Approach 1:
The patent merges the ferroelectric pattern formation with the existing three-dimensional stacking process. The ferroelectric patterns are integrated into the vertical stack along with the channel patterns, gate electrodes, and source/drain structures. This merging approach incorporates the ferroelectric functionality without requiring separate fabrication steps, thereby improving electrical characteristics while minimizing the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances the reliability and electrical characteristics of the semiconductor device by preventing interfacial property deterioration and improving sub-threshold swing properties and lowering operation voltage.
Implementation Method 1
a first ferroelectric pattern interposed between the substrate and the first channel pattern
Implementation Method 2
a gate electrode disposed on the first and second channel patterns
Data Source
AI summary
A three-dimensional semiconductor device is provided. The device includes: a first active region on a substrate, the first active region including a first source/drain pattern that is connected to a first channel pattern; a second active region stacked on the first active region, and including a second source/drain pattern that is connected to a second channel pattern; a gate electrode disposed on the first and second channel patterns; and a first ferroelectric pattern interposed between the substrate and the first channel pattern. The first channel pattern includes a first semiconductor pattern and a second semiconductor pattern, which are spaced apart from each other in a vertical direction perpendicular to a top surface of the substrate. The first ferroelectric pattern is interposed between the substrate and the first semiconductor pattern. The gate electrode includes a first gate electrode interposed between the first and second semiconductor patterns.