3D Memory Charge Storage Structure for Vertical Cell Leakage Reduction
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in reducing leakage current between vertically neighboring memory cells, which affects the performance and efficiency of memory storage.
Innovation Solution
The implementation of a three-dimensional memory device structure featuring an alternating stack of insulating and electrically conductive layers, with discrete charge storage elements and dielectric material portions vertically spaced, a tunneling dielectric layer, and a semiconductor channel, which reduces leakage current through specific manufacturing processes such as forming memory openings, sacrificial fill structures, and replacing sacrificial material layers with conductive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional vertical NAND strings are used to increase storage density, then storage capacity is improved, but leakage current between vertically neighboring memory cells increases
Solution Approach 1:
The memory cell is segmented into discrete charge storage elements separated by dielectric material portions. This segmentation creates electrical isolation between vertically neighboring cells, preventing leakage current while maintaining high storage density through the three-dimensional vertical structure.
Solution Approach 2:
Dielectric material portions serve as intermediary elements between charge storage elements at different vertical levels. These intermediary dielectric layers block electrical leakage paths while allowing the vertical stacking architecture to maintain high storage capacity.
2Object-generated harmful factors
If discrete charge storage elements are implemented to reduce leakage current, then electrical isolation between cells is improved, but device structure complexity increases
Solution Approach 1:
The alternating stack of insulating and conductive layers is merged into a single integrated three-dimensional structure. This merging approach reduces manufacturing complexity by forming discrete charge storage elements and dielectric material portions within the same fabrication process, while still achieving electrical isolation between cells.
Solution Approach 2:
The alternating stack structure serves multiple functions simultaneously: it provides electrical isolation between vertically neighboring cells, maintains mechanical structural integrity, and enables high-density storage. This multi-functionality reduces overall device complexity despite the presence of discrete charge storage elements.
3Quantity of substance
If an alternating stack of insulating and conductive layers is formed to create discrete charge storage elements, then charge storage capability is improved, but manufacturing process complexity increases
Solution Approach 1:
The alternating stack of insulating and conductive layers is formed as a preliminary structure before creating the final discrete charge storage elements. This preliminary alternating stack provides a ready-made template and isolation framework that simplifies subsequent processing steps for forming individual charge storage elements and dielectric material portions.
Solution Approach 2:
Discrete charge storage elements and dielectric material portions are nested within the alternating stack structure. This nesting approach allows the complex three-dimensional structure to be built incrementally, with each layer nested within the previous alternating stack, thereby simplifying the overall manufacturing process while maintaining high charge storage capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively minimizes leakage current between memory cells, enhancing the performance and efficiency of the memory device by allowing for the formation of multilevel memory structures like three-dimensional monolithic NAND strings.
Implementation Method 1
a tunneling dielectric layer in contact with the first vertical stack and the second vertical stack
Data Source
AI summary
An alternating stack of insulating layers and electrically conductive layers is formed over a substrate, and a memory opening vertically extends through the alternating stack. The memory opening is laterally expanded at levels of the insulating layers. At least one blocking dielectric layer is formed in the memory opening. A first vertical stack of discrete charge storage elements is formed at levels of the electrically conductive layers. A second vertical stack of discrete dielectric material portions is formed at the levels of the insulating layers. A tunneling dielectric layer is formed over the first vertical stack and the second vertical stack. A vertical semiconductor channel is formed on the tunneling dielectric layer.