3D Memory Structure with Spaced Charge-Trap Layers for Data Retention

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Solution Overview

Problem

In three-dimensional memory devices, interference between consecutive memory cells in the vertical direction leads to deterioration of retention characteristics, as the threshold voltage of programmed memory cells is not maintained effectively.

Innovation Solution

A memory device structure is designed with a channel layer surrounded by a blocking layer, multiple charge trap layers spaced apart and arranged along the blocking layer, and tunnel insulating layers positioned between the charge trap layers and gate lines, reducing interference by separating adjacent charge trap layers and maintaining electron trapping until an erase operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If charge trap layers are arranged closely in vertical stacking to increase storage density, then device integration is improved, but interference between consecutive memory cells increases and retention characteristics deteriorate

Engineering Contradiction:

Improvestorage densityVSAvoidretention characteristics

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

A tunnel insulating layer is introduced as an intermediary between adjacent charge trap layers. This layer physically separates the charge trap layers while allowing controlled electron tunneling during programming and erasing operations, thereby reducing direct interference between consecutive memory cells and improving data retention characteristics

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The charge trap layers are segmented by spacing them apart and inserting tunnel insulating layers between them. This segmentation reduces the interference between consecutive memory cells in the vertical direction while maintaining high storage density through multiple stacked layers

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If multiple charge trap layers are stacked vertically to increase capacity, then storage capacity is improved, but interference between adjacent layers causes threshold voltage instability

Engineering Contradiction:

Improvestorage capacityVSAvoidthreshold voltage stability

Core Design Contradiction:

Quantity of substanceVSStability of the object's composition

Solution Approach 1:

The tunnel insulating layer acts as a mediator between stacked charge trap layers, enabling controlled electron transport during programming and erasing while preventing unwanted electron migration between adjacent layers during retention, thus stabilizing threshold voltage

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The structure transitions to three-dimensional vertical stacking of charge trap layers separated by tunnel insulating layers. This multi-layer vertical arrangement increases storage capacity while the insulating layers prevent interference, maintaining threshold voltage stability

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution improves data retention characteristics by stabilizing electron trapping and maintaining threshold voltage, enhancing the retention performance of memory cells.

Implementation Method 1

tunnel insulating layers, each of the plurality of tunnel insulating layers contacting a different one of the plurality of charge trap layers

Methodology Applied

Scientific EffectTunneling:

Implementation Method 2

multiple charge trap layers spaced apart and arranged along the blocking layer... maintaining electron trapping until an erase operation

Methodology Applied

Scientific EffectElectron trapping:

Data Source

PatentUS20250331180A1Memory device, method of manufacturing memory device, and method of operating memory device

Publication Date: 2025.10.23 SK HYNIX INC

AI summary

An embodiment includes a memory device, a method of manufacturing the memory device, and a method of operating the memory device. The memory device includes a channel layer, a blocking layer surrounding the channel layer, a plurality of charge trap layers spaced apart from each other and arranged along a surface of the blocking layer, a plurality of tunnel insulating layers, each of the plurality of tunnel insulating layers contacting a different one of the plurality of charge trap layers, and a plurality of gate lines, each of the plurality of gate lines contacting a different one of the plurality of tunnel insulating layers, and each of the plurality of tunnel insulating layers is positioned between a different one of the plurality of charge trap layers and a different one of the plurality of gate lines.