3D Chip Stack Backside Metallization for TSV-Free Power Routing
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Solution Overview
Problem
Conventional 3D chip stacking technologies face limitations due to clustered through-silicon vias (TSVs) that occupy silicon area, disrupt layout, and limit signal and power fan-out, necessitating improvements in power distribution and heat dissipation.
Innovation Solution
Implementing back side metallization with smaller, distributed backside vias and thermal grids to replace TSVs, enabling efficient power and signal distribution, and improved heat conduction through the use of backside pass-through vias and thermal mitigation mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) are used for power and signal feed-through in 3D stacking, then electrical connectivity between chips is achieved, but silicon area is consumed due to keep-out regions and pitch distance requirements
Solution Approach 1:
The patent utilizes the back side of the silicon die as an additional dimension for via placement. By forming vias on the back side of the die rather than only on the front side, the design distributes via locations across both surfaces, effectively doubling the available area for via placement and reducing the area consumption per via on the front side.
Solution Approach 2:
The patent segments the via placement into two separate locations: front side vias and back side vias. This segmentation allows power and signal feed-through to be achieved through multiple distributed via locations rather than requiring large keep-out regions around fewer vias, thereby reducing the total silicon area consumed.
2Power
If TSVs are clustered on the die for power distribution, then power feed-through is achieved, but layout flexibility and signal fan-out are limited
Solution Approach 1:
By adding back side via placement as another dimension, the patent enables power distribution networks to be formed with greater layout flexibility. Designers can distribute vias more evenly across both front and back sides, improving signal fan-out and reducing the need for clustered via arrangements.
Solution Approach 2:
The patent applies local quality by allowing different via densities and configurations in different regions of the die. Front side and back side vias can be independently optimized for their respective local requirements, enabling better adaptation to specific power and signal distribution needs in different areas of the chip.
3Temperature
If back side metallization is implemented, then heat dissipation is improved, but additional manufacturing process steps are required
Solution Approach 1:
The back side metallization layer serves multiple functions simultaneously: it provides thermal dissipation pathways and enables via formation for electrical connectivity. By making the metallization layer multi-functional, the patent justifies the additional manufacturing steps as they deliver dual benefits rather than requiring separate dedicated thermal management structures.
Solution Approach 2:
The patent merges the thermal management function and electrical connectivity function into a single integrated structure. The back side metallization layer and via structures serve both as heat dissipation pathways and as electrical interconnects, combining two previously separate functions into one unified solution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances silicon area utilization, improves power management, reduces layout disruptions, and optimizes heat dissipation, leading to more efficient 3D stacking configurations.
Implementation Method 1
Back side metallization provides an electrically conductive contact and/or a heat conductive contact for the dies
Implementation Method 2
Back side metallization provides an electrically conductive contact and/or a heat conductive contact for the dies
Data Source
AI summary
Three-dimensional integrated circuit stack configurations include a bottom die configured with bottom die back side metallization and bottom die front side metallization, and a top die configured with metal layers adjacent to the bottom die front side metallization. The bottom die is configured to pass power from the bottom die back side metallization to the metal layers of the top die by way of back side pass-through vias formed in dummy cells interspersed among active logic cells of the bottom die.