3D Chip Bonding Structure With Compact Layer for Void-Free Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Chip warpage and poor surface quality during chip-to-chip bonding in 3D integrated circuit layouts adversely affect electrical connections, leading to performance issues.
Innovation Solution
A semiconductor structure design incorporating a compact layer made of polymer or glass with nitrogen, hydrogen, or oxygen dopants, which provides excellent reflow capability, and a cap layer to prevent gas diffusion, ensuring void-free bonding and improved surface quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chip-to-chip bonding is performed in 3D integrated circuit layouts, then circuit density and performance are improved, but chip warpage occurs causing bonding failure
Solution Approach 1:
The patent applies preliminary action by forming a compact layer and cap layer structure before the chip bonding process. The compact layer is deposited over the interconnect structure and RDL, followed by a cap layer, creating a pre-prepared structure that prevents warpage during subsequent bonding operations. This advance preparation ensures bonding reliability is maintained while achieving high circuit density through 3D integration.
2Reliability
If chip-to-chip bonding is performed in 3D integrated circuit layouts, then electrical connections are enhanced, but surface quality deteriorates adversely affecting connection performance
Solution Approach 1:
The patent applies parameter changes by modifying the physical and chemical properties of the compact layer through dopant incorporation (nitrogen, hydrogen, or oxygen). These compositional changes improve the reflow capability of the compact layer, enabling it to maintain excellent surface quality during the bonding process. The cap layer further protects the surface, ensuring that electrical connection performance is not adversely affected.
3Reliability
If compact layer with dopants is used, then reflow capability is improved preventing voids, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates dopants (nitrogen, hydrogen, or oxygen) into the compact layer to modify its material properties, specifically improving reflow capability. This parameter change enables the compact layer to flow and fill voids effectively during bonding, ensuring bonding integrity. While this adds a dopant incorporation step to the manufacturing process, the improvement in bonding reliability justifies the increased complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively prevents chip warpage and enhances surface quality, ensuring reliable chip-to-chip bonding and improved electrical connections.
Implementation Method 1
the compact layer has excellent reflow capability
Implementation Method 2
a cap layer to prevent gas diffusion
Data Source
AI summary
A semiconductor structure includes a first chip and a second chip bonded to the first chip. The first chip includes a first semiconductor substrate, a first multi-level interconnect structure over the first semiconductor substrate, a first redistribution layer (RDL) over a conductive line of the first multi-level interconnect structure, a compact layer over the first RDL and the first multi-level interconnect structure, a cap layer over the compact layer, and a metal pad on the first RDL. The second chip includes a second semiconductor substrate, a second multi-level interconnect structure over the second semiconductor substrate, and conductive structure extending from the second multi-level interconnect structure to the metal pad.