3D Chip Shared Interconnect Layout for Clock Distribution
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Solution Overview
Problem
The limitations of Moore's Law, as semiconductor fabrication advances reach the maximum number of transistors that can be defined on a semiconductor substrate, necessitate innovative approaches to increase transistor density in IC chips.
Innovation Solution
A three-dimensional (3D) circuit is formed by stacking two or more integrated circuit (IC) dies to share interconnect layers for power, clock, and data-bus signals, utilizing direct bonding techniques like DBI to establish high-density connections between top interconnect layers, allowing for orthogonal wiring directions that reduce capacitive load and optimize signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more interconnect layers are added to a single IC die to accommodate more transistors, then transistor capacity increases, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of interconnect layers on a single die to a three-dimensional stacked configuration where multiple IC dies are vertically arranged. This dimensional change allows the system to accommodate more transistors by adding vertical stacking rather than increasing horizontal layer complexity, thereby resolving the contradiction between transistor quantity and device complexity.
Solution Approach 2:
The patent merges multiple IC dies into a single stacked structure where adjacent dies share common interconnect layers. By combining multiple dies and their interconnect systems into an integrated stack, the overall system achieves higher transistor capacity without proportionally increasing the number of distinct interconnect layers, as shared layers serve multiple dies simultaneously.
2Ease of operation
If each IC die has its own separate interconnect layers for power and clock signals, then signal routing is simplified, but the number of interconnect layers and space consumption increase
Solution Approach 1:
Adjacent IC dies in the stack share common interconnect layers for power, clock, and data-bus signals. This merging of interconnect resources between dies reduces the total number of interconnect layers required compared to having completely separate interconnect systems for each die, while still maintaining organized signal routing through the shared infrastructure.
Solution Approach 2:
The shared interconnect layers serve multiple functions and multiple dies simultaneously. A single interconnect layer can provide power or clock signals to multiple adjacent dies, making the interconnect structure universal rather than dedicated to a single die. This multi-functionality reduces the overall number of interconnect layers needed while maintaining comprehensive signal distribution.
3Quantity of substance
If IC dies are stacked to share interconnect layers, then transistor density increases and space is freed up, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs vertical stacking of IC dies in the third dimension, which increases transistor density by utilizing vertical space rather than expanding the horizontal chip footprint. This dimensional transition allows higher integration while the shared interconnect architecture helps manage the manufacturing precision challenges inherent in multi-die stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases transistor density by reducing the number of interconnect layers needed, shortening signal paths, and enhancing signal integrity, while freeing up space for other circuits, thus optimizing cost and performance in chip stack systems.
Implementation Method 1
a direct bonding process that establishes direct-contact metal-to-metal bonding, oxide bonding, or fusion bonding between these two sets of interconnect layers
Implementation Method 2
a direct bonding process that establishes direct-contact metal-to-metal bonding, oxide bonding, or fusion bonding between these two sets of interconnect layers
Implementation Method 3
a direct bonding process that establishes direct-contact metal-to-metal bonding, oxide bonding, or fusion bonding between these two sets of interconnect layers
Data Source
AI summary
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.