3D Chip-Stack Clock Synchronization Using TSV Delay Compensation
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Solution Overview
Problem
Existing clock distribution systems for 3-D chip stacks face challenges in synchronizing clock signals across multiple chips, particularly when using through-silicon vias (TSVs), as prior methods are limited in handling clock skew and are not effective for multi-chip assemblies where signals must travel through many levels.
Innovation Solution
A clock distribution system where a central reference clock in the middle chip generates local clock signals for each individual chip using PLL-based local clocks, with delay compensation through TSVs and on-chip metal wirings, and a multiplexer for phase locking, ensuring minimal clock skew and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a prior art clock distribution network connects two substrates face-to-face using flip-chip technology, then clock signals can be distributed with minimal skew between two chips, but the method cannot handle clock skew when a plurality of chips are assembled in 3-D stack where clock signals must travel through many levels of chips and TSVs
Solution Approach 1:
The patent divides the clock distribution system into multiple independent segments, each chip containing its own PLL (Phase-Locked Loop) that independently generates and synchronizes its clock signal. This segmentation allows each chip to handle its own clock skew independently rather than relying on a single centralized clock distribution network that would fail in multi-chip configurations.
Solution Approach 2:
The patent introduces TSVs (Through-Silicon Vias) as intermediary elements to carry clock signals vertically between chips in the 3-D stack. These TSVs serve as dedicated clock distribution pathways that penetrate through multiple chip levels, enabling synchronized clock delivery to each chip's PLL while compensating for path length variations.
2Productivity
If chips are stacked in 3-D using TSVs to reduce die-to-die signal transmission distance and increase number of links, then packaging density and performance are improved, but synchronization of clock signal among various chips becomes critical and difficult
Solution Approach 1:
The patent implements preliminary clock signal distribution through TSVs before the actual data processing operations begin. Each chip's PLL is pre-synchronized using the vertically transmitted clock signals, ensuring that all chips are ready to operate in sync from the start of their operational cycle, thus preventing synchronization issues during high-speed data processing.
Solution Approach 2:
The patent employs feedback mechanisms within each chip's PLL to continuously monitor and adjust its local clock signal based on the reference clock received through TSVs. This closed-loop feedback ensures that any drift or skew is automatically corrected, maintaining reliable synchronization across all chips in the 3-D stack even under varying operational conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system achieves synchronized clock signals across all chips in a 3-D stack with minimal skew and jitter, enabling high-performance multi-processor systems by using a central reference clock and PLL-based local clocks with precise delay compensation and multiplexer-based phase locking.
Implementation Method 1
A clock distribution system where a central reference clock in the middle chip generates local clock signals for each individual chip using PLL-based local clocks
Implementation Method 2
delay compensation using TSVs and on-chip metal wirings, wherein designated number of TSVs and a predetermined length of on-chip metal wires are used to provide a route between the master clock and the local VCO's of each individual chip
Implementation Method 3
an output from a charge pump in the master clock is linked to the local VCO located in each individual chip, generating local clock signals in the corresponding chips in the stack. The output of each VCO in each chip is linked by way of its corresponding divider to a multiplexer (MUX) in the middle chip, wherein the MUX scans through all the channels in order to periodically lock the clock phase of each chip within the stack
Data Source
AI summary
A central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews.