3D Chip Bonding Structure With Compact Layer Against Warpage
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Solution Overview
Problem
Chip warpage and poor surface quality during chip-to-chip bonding in 3D integrated circuit layouts adversely affect electrical connections, leading to performance issues.
Innovation Solution
A semiconductor structure with a compact layer made of polymer or glass, containing nitrogen, hydrogen, or oxygen dopants, is introduced to fill voids and improve bonding, combined with a cap layer to prevent gas diffusion, enhancing the surface quality and preventing warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chip-to-chip bonding is performed in 3D integrated circuit layouts, then circuit density and performance are improved, but chip warpage and poor surface quality occur leading to bonding failure
Solution Approach 1:
The patent applies preliminary action by forming a compact layer filled with polymer or glass material before the chip bonding process. This compact layer is deposited over the interconnect structure and RDL in advance, filling voids and preventing warpage development during subsequent bonding operations, thereby ensuring bonding reliability while maintaining high circuit density
Solution Approach 2:
The patent changes material parameters by introducing a compact layer with specific physical properties (polymer or glass material with appropriate viscosity and filling characteristics). This material parameter change enables the layer to flow into and fill voids in the interconnect structure, preventing warpage and improving surface quality for reliable bonding
2Reliability
If multi-level interconnect structures with RDL are used, then electrical connection capability is improved, but void formation and warpage occur affecting surface quality
Solution Approach 1:
The patent addresses void formation in multi-level interconnect structures by using a compact layer made of polymer or glass material that can flow into and fill porous spaces and voids within the interconnect structure. This material effectively consolidates the internal structure, eliminating air pockets while maintaining the electrical connection capability of the multi-level RDL architecture
Solution Approach 2:
The patent employs composite material approach by combining the compact layer material (polymer or glass) with the existing interconnect structure and RDL. This composite structure integrates the filling material with the conductive elements, creating a unified structure that maintains electrical functionality while improving surface quality and preventing warpage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents void formation and warpage, improving the surface quality for bonding and ensuring reliable electrical connections in 3D integrated circuits.
Implementation Method 1
since the compact layer is located on the first RDL and the first multi-level interconnect structure and the compact layer has a good reflow (or filling) capability, the compact layer adjacent to the first RDL is free from void
Implementation Method 2
combined with a cap layer to prevent gas diffusion
Data Source
AI summary
A semiconductor structure includes a first chip and a second chip bonded to the first chip. The first chip includes a first semiconductor substrate, a first multi-level interconnect structure over the first semiconductor substrate, a first redistribution layer (RDL) over a conductive line of the first multi-level interconnect structure, a compact layer over the first RDL and the first multi-level interconnect structure, a cap layer over the compact layer, and a metal pad on the first RDL. The second chip includes a second semiconductor substrate, a second multi-level interconnect structure over the second semiconductor substrate, and conductive structure extending from the second multi-level interconnect structure to the metal pad.