3D Multi-Core Chip Stacking for Shorter Die-to-Die Links
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Solution Overview
Problem
Current die-to-die interfaces in system-level chips face signal attenuation and speed reduction due to long transfer paths through interposer layers, which cannot meet the requirements for high-intensity computing.
Innovation Solution
A multi-core chip design where the first and second core layers are vertically stacked, enabling data transfer between layers through transceiver circuits without an interposer layer, significantly shortening the transfer path and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two modules or dies are connected through an interposer layer, then the die-to-die interface can provide data transfer functionality, but the transfer path becomes too long causing signal attenuation and speed reduction
Solution Approach 1:
The patent transitions from a planar connection architecture to a three-dimensional stacked architecture. Multiple dies are arranged in vertical layers and connected through through-silicon vias (TSVs), changing the connection dimension from 2D to 3D. This dimensional change enables short-distance communication between stacked dies while maintaining scalability for multiple modules, effectively resolving the contradiction between connection functionality and path length.
2Adaptability or versatility
If chip design uses maximum mask size, then more functions can be integrated, but the chip must be divided into multi-chip modules requiring ultra-short distance connections
Solution Approach 1:
The patent merges multiple independent chip modules into a unified three-dimensional integrated structure. By stacking dies vertically and providing inter-layer connection structures, the system achieves high-bandwidth communication between modules while maintaining modular design benefits. This merging approach enables complex functionality across multiple dies without requiring excessive external interconnections, resolving the contradiction between functional integration and structural complexity.
Data Source
AI summary
The present disclosure relates to a multi-core chip, an integrated circuit device, a board card and a manufacturing method thereof, where the computing device of the present disclosure is included in an integrated circuit device, and the integrated circuit device includes a universal interconnection interface and other processing devices. The computing device interacts with other processing devices to jointly complete computing operations specified by the user. The integrated circuit device also includes a storage device, which is respectively connected to the computing device and other processing devices and is used for storing data of the computing device and other processing devices.