3D Inter-Chip Capacitive Receiver With Double-Feedback Recovery
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Solution Overview
Problem
Existing asynchronous capacitive interconnection systems for 3D inter-chip communication face challenges in minimizing power consumption while maintaining high performance and reliability, particularly due to significant attenuation in capacitive transmission channels, which requires high-gain receiver circuits and increased power consumption.
Innovation Solution
An asynchronous interconnection system featuring a receiver circuit with a double feedback loop and a transmitter circuit as a simple buffer, allowing for voltage signal reconstruction and maintaining a high impedance state, thereby reducing power consumption and optimizing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-gain receiver circuits are used to compensate for attenuation in capacitive transmission channels, then signal reception performance is improved, but power consumption increases
Solution Approach 1:
The patent implements a double feedback loop architecture in the receiver circuit. The first feedback loop feeds back the recovered voltage signal to control the recovery stage, while the second feedback loop feeds back the state control signal to regulate the impedance switching. This feedback mechanism enables automatic adjustment and optimization of the receiver operation, maintaining high signal reception performance while minimizing power consumption through adaptive control rather than continuous high-gain operation.
Solution Approach 2:
The receiver circuit dynamically switches between different impedance states (high impedance and low impedance) based on the received signal conditions. The state control stage dynamically adjusts the receiver's operating state in response to signal attenuation variations, enabling the circuit to adapt its power consumption and gain characteristics in real-time. This dynamic operation allows the receiver to achieve high performance only when necessary while consuming minimal power during stable transmission periods.
2Device complexity
If simple buffer transmitter circuits are used, then device complexity is reduced, but voltage signal attenuation increases
Solution Approach 1:
The patent introduces an intermediary capacitive coupling channel between the simple buffer transmitter and the sophisticated receiver. This capacitive channel acts as a mediator that transfers the voltage signal from the low-complexity transmitter to the receiver, which then compensates for the attenuation through its double feedback loop architecture. The intermediary channel enables signal transmission while allowing the transmitter to remain simple and the receiver to handle the signal quality.
Solution Approach 2:
The receiver circuit changes its operating parameters (impedance level, gain state) based on the attenuated signal conditions. By dynamically adjusting these parameters through the feedback loops, the receiver compensates for the voltage signal attenuation caused by the simple transmitter and capacitive channel, maintaining adequate signal levels without requiring a complex transmitter design.
3Reliability
If receiver circuits operate continuously to maintain signal detection, then reliability is improved, but static current consumption increases
Solution Approach 1:
The receiver circuit employs periodic action by switching between active detection states and high-impedance standby states. The state control stage periodically activates the recovery stage only when signal transitions are detected, rather than maintaining continuous operation. This periodic operation maintains detection reliability for asynchronous signals while dramatically reducing static current consumption during idle periods when no data transmission occurs.
Solution Approach 2:
The receiver circuit uses the incoming signal itself to trigger its activation. The capacitive coupling channel naturally couples signal transitions from the transmitter to the receiver, and these transitions automatically trigger the feedback loops to activate the recovery stage. The circuit serves itself by using the presence of data to activate its own operation, eliminating the need for external control signals or continuous power consumption to maintain readiness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed system achieves low power consumption and high performance functionality by minimizing static current and area requirements, ensuring efficient data exchange with improved timing margins and reduced voltage swing, thus overcoming the limitations of prior art.
Implementation Method 1
a transmitter circuit and a receiver circuit inserted between a first and a second voltage reference and having respective transmitter and receiver nodes coupled in a capacitive manner
Data Source
Figure 1~2
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Figure 4
AI summary
The present invention relates to a asynchronous interconnection system (10) comprising a transmitter circuit (11) and a receiver circuit (12) inserted between inserted between respective first and second voltage references (Vcctx, GNDtx - Vccrx, GNDrx) and having respective transmitter and receiver nodes (TX, RX) coupled in a capacitive manner. Advantageously according to the invention, the receiver circuit (12) comprises: - a recovery stage (13) inserted between the first and second voltage references (Vccrx, GNDrx) of the receiver circuit (12) and connected to the receiver node (RX); and - a state control stage (14), in turn inserted between the first and second voltage references (Vccrx, GNDrx) of the receiver circuit (12) connected to the recovery stage (13) correspondence with a first feedback node (X) providing a first control signal (Recovery Enable) and having a second feedback node (Z*) connected in a feedback manner to the recovery stage (13). The recovery stage (13) comprises a first feedback loop (Loop 1) connected to the first feedback node (X) and acting in such a way to recover a received voltage signal and a feedback loop (Loop2) connected to the second feedback node (Z*) of the state control stage (14) and acting in such a way to deactivate the recovery feedback on the receiver node (RX) and guarantee that the receiver node (RX) is let in a high impedance state.