3D Chip Memory Management Unit for Dynamic Allocation
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Solution Overview
Problem
Current mobile terminal memory systems face challenges such as ad-hoc memory usage, difficulty in secure runtime allocation, high power consumption, and limited scalability due to dedicated memory designs, which lead to performance bottlenecks and increased costs, especially with the rising complexity of multiprocessor architectures.
Innovation Solution
A 3D chip arrangement with a centralized memory management unit that dynamically allocates and deallocates memory for subsystems, using face-to-face connections and silicon-through VIAs for wide buses, enabling efficient memory access and hiding the physical memory implementation from software, thus providing secure and scalable memory management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated memories are reserved for each subsystem, then data security and reliability are improved, but memory efficiency and scalability deteriorate
Solution Approach 1:
The memory system is segmented into multiple memory banks that can be independently accessed by different subsystems. The memory management unit divides the global memory space into bank-specific address spaces, allowing each subsystem to have dedicated access to specific memory regions while sharing the physical memory infrastructure. This segmentation provides both security (isolated access) and efficiency (shared resources).
Solution Approach 2:
A memory management unit acts as an intermediary between subsystems and the global memory. It translates logical addresses from multiple subsystems into physical addresses in the memory banks, enforcing access control and managing memory allocation dynamically. This mediator enables secure runtime allocation while maintaining high memory efficiency through centralized management.
2Productivity
If memory bus frequency is increased to improve bandwidth, then memory performance is improved, but power consumption increases
Solution Approach 1:
The patent transitions from increasing frequency (time dimension) to increasing parallelism (spatial dimension) for bandwidth improvement. Multiple memory banks are accessed simultaneously by multiple subsystems through a scaled memory bus, achieving higher total bandwidth without proportionally increasing frequency and thus avoiding quadratic power consumption increases.
Solution Approach 2:
The memory system dynamically allocates memory resources and adjusts bus utilization based on actual subsystem needs. The memory management unit can activate or deactivate specific memory banks and adjust the number of active data buses, allowing the system to scale bandwidth consumption according to actual performance requirements rather than maintaining maximum frequency constantly.
3Productivity
If memory bus width is increased to improve bandwidth, then memory performance is improved, but device complexity and packaging difficulty increase
Solution Approach 1:
Instead of using a single wide memory bus, the system segments the data path into multiple narrower buses, each connecting to specific memory banks. This segmentation reduces the complexity of individual connections while achieving equivalent or superior total bandwidth through parallel access to multiple banks, simplifying packaging and routing requirements.
4Productivity
If multiple levels of cache hierarchy are added to improve memory bandwidth, then memory performance is improved, but power consumption and device complexity increase
Solution Approach 1:
The patent merges the functions of multiple cache levels and memory interfaces into a unified memory system with multiple banks. Instead of having separate L1, L2, and L3 caches each with their own interfaces, the system provides a single scaled memory interface that directly accesses multiple memory banks, achieving high bandwidth without the redundant complexity and power consumption of multiple cache hierarchies.
Data Source
AI summary
Systems, apparatuses and methods involving centralized memory management capable of allocating and de-allocating memory for all subsystems dynamically. One embodiment involves a base substrate, a logic die(s) on the base substrate and having a subsystem(s), a memory die(s) having a memory module(s), a memory management unit, a first data interface connecting the memory management unit with the at least one logic die, a second data interface connecting the memory management unit with the at least one memory die, a configuration interface connecting the memory management unit with the at least one memory die, where the configuration interface includes face-to-face connections, a control interface connecting the memory management unit with the at least one logic die, where the memory die(s) and the logic die(s) are arranged in a stacked configuration on the base substrate, and the memory management unit is adapted for managing memory accesses from the subsystem(s) by negotiating an allowed memory access with the subsystem(s) via the control interface and configuring the at least one memory module according to the allowed memory access via the configuration interface.