3D Chip Package with Non-Vertical Side Walls for Batch Singulation
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Solution Overview
Problem
Existing chip packaging technologies face challenges in maintaining high-bandwidth, low-power, and low-cost interconnects between chips as they scale to smaller dimensions, particularly due to difficulties in accurate mechanical alignment and increased complexity in three-dimensional integration.
Innovation Solution
A chip package design featuring chips with non-vertical side-wall angles, facilitated by a batch processing technique that includes wet or dry etching and thinning of wafers, allowing for precise mechanical and electrical coupling using proximity-communication connectors and underfill materials, which reduces chipping damage during the singulation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional individually packaged chips are used with printed circuit board connections, then manufacturing is simpler, but inter-chip communication bandwidth and data rate deteriorate at higher operating frequencies
Solution Approach 1:
Multiple chips are integrated into a single multi-chip module package, merging individual chip functions into a unified 3D structure. This combines the manufacturing simplicity of individual chips with the high-performance interconnects of direct chip-to-chip coupling, eliminating the need for external PCB traces while maintaining ease of module-level manufacturing.
Solution Approach 2:
The patent transitions from planar 2D chip arrangements on PCBs to three-dimensional vertical stacking of chips. This dimensional change enables significantly shorter inter-chip interconnect paths, reducing signal propagation delays and allowing high-bandwidth communication at higher frequencies while maintaining compact form factor.
2Reliability
If dense inter-chip connections are implemented in MCM with pitch of 10-100 μm, then inter-chip communication bandwidth is improved, but mechanical alignment precision requirements worsen
Solution Approach 1:
Alignment features and bonding structures are prepared in advance during chip fabrication, with pre-defined pad geometries and positioning structures. This preliminary preparation of alignment references enables accurate positioning during assembly, achieving the required mechanical alignment precision for dense inter-chip connections without requiring complex real-time adjustment mechanisms.
3Productivity
If chips are singulated using conventional dicing process, then manufacturing throughput is maintained, but chipping damage to dielectric layers increases
Solution Approach 1:
The patent replaces the mechanical dicing process with a chemical etching process for chip singulation. This substitution eliminates the mechanical contact and vibration that cause chipping damage to dielectric layers, while maintaining high manufacturing throughput through batch processing of multiple chips simultaneously. The chemical process provides cleaner separation without physical trauma to the chip structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances manufacturing throughput and yield, reduces costs, and enables dense 3D integration of disparate technology platforms, while minimizing chipping damage and improving alignment accuracy, thus addressing the limitations of conventional packaging methods.
Implementation Method 1
facilitated by a batch processing technique that includes wet or dry etching
Implementation Method 2
facilitated by a batch processing technique that includes wet or dry etching
Implementation Method 3
thinning of wafers
Implementation Method 4
The mechanical coupling may include an underfill material that selectively couples the first surface to the second surface
Data Source
AI summary
A chip package is described which includes a first chip having a first surface and first sides having a first side-wall angle, and a second chip having a second surface and second sides having a second side-wall angle, which faces and is mechanically coupled to the first chip. The chip package is fabricated using a batch process, and the chips in the chip package were singulated from their respective wafers after the chip package is assembled. This is accomplished by etching the first and second side-wall angles and thinning the wafer thicknesses prior to assembling the chip package. For example, the first and/or the second side walls can be fabricated using wet etching or dry etching. Therefore, the first and/or the second side-wall angles may be other than vertical or approximately vertical.