3D Chip Packaging Structure Without Silicon Bridge Interconnects
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Solution Overview
Problem
Current semiconductor packaging structures are complex and hinder high-speed, small-volume interconnection between chips, requiring silicon bridges that increase costs and prolong transmission paths, making it difficult to achieve improved communication speeds.
Innovation Solution
A packaging structure and method where a substrate with a chipset featuring stacked first chips, with the bottom chip exposed, allows direct electrical connection to a second chip without a bridge, simplifying the structure and shortening the transmission path by using the bottom chip for interconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If silicon bridge is used to realize interconnection between chips, then heterogeneous chip packaging is achieved, but packaging structure becomes complex and communication speed decreases
Solution Approach 1:
The patent removes the silicon bridge component from the packaging structure, allowing chips to be directly connected to the substrate through bonding pads. This extraction of the intermediary bridge element simplifies the packaging structure while maintaining heterogeneous chip packaging capability through direct bonding interfaces.
Solution Approach 2:
The patent employs asymmetric chip stacking arrangements where chips of different types and sizes can be positioned at different heights and orientations relative to the substrate. This asymmetric configuration enables heterogeneous integration without requiring symmetric bridge connections, thereby simplifying the overall packaging structure.
2Reliability
If silicon bridge is used for chip interconnection, then chip connectivity is achieved, but transmission path length increases
Solution Approach 1:
By removing the silicon bridge from the interconnection path, the patent creates a direct transmission path from chip bonding pads to substrate contact pads. This eliminates the additional transmission distance through the bridge structure, reducing overall path length while maintaining reliable electrical connectivity.
Solution Approach 2:
The patent transitions from a planar interconnection approach through bridges to a three-dimensional direct bonding configuration. Chips are stacked vertically with direct bonding interfaces, creating shorter transmission paths through the vertical dimension rather than extending horizontally through bridge structures.
3Adaptability or versatility
If conventional packaging structure is used, then chip integration is achieved, but communication speed between chips is limited
Solution Approach 1:
The patent implements three-dimensional chip stacking with direct bonding interfaces, replacing conventional planar packaging. This vertical integration approach shortens signal transmission paths and reduces parasitic effects, thereby increasing communication speed between stacked chips while maintaining integration capability.
Solution Approach 2:
By eliminating the silicon bridge intermediary, the patent creates direct electrical pathways between chips and substrate. This removal of intermediate connection structures reduces signal attenuation and propagation delays, enabling higher communication speeds while preserving chip integration functionality.
Data Source
AI summary
This disclosure relates to packaging method and a packaging structure. The packaging structure includes: a substrate, including a bonding surface, a chipset, bonded to the bonding surface and including a plurality of first chips stacked along a longitudinal direction, where the first chip adjacent to the substrate is used as a bottom chip, each of the rest of the first chips is used as a top chip; and a second chip, bonded to the bottom chip exposed from the top chip and to the bonding surface on a side of the chipset, where the second chip, the bottom chip, the top chip, and the substrate are electrically connected, and a projection of the second chip and a projection of the bottom chip on a projection plane parallel to the bonding surface partially overlap. The present disclosure helps improve a speed of communication between chips.