3D Chip Packaging Structure for Dense High-Speed Interconnects
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Solution Overview
Problem
Conventional chip manufacturing technologies face challenges in achieving high-speed and small-volume interconnection between chips, limiting the realization of large size integrated circuits with improved performance.
Innovation Solution
A packaging structure and method that includes device chips with interconnection structures, an interconnect chip bonded to the device chip and packaging layers, and via interconnection structures to reduce the distance between interconnect ports, increasing interconnection density and communication speed, while using a single carrier to simplify the process and reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If smaller integrated circuits with Si bridge chips are used to realize interconnection between chips, then heterogeneous chip packaging is achieved, but the interconnection performance between chips needs to be improved
Solution Approach 1:
The patent transitions from planar interconnection to three-dimensional vertical interconnection by stacking device chips and interconnect chips in multiple layers. The via interconnection structure penetrates through packaging layers to establish vertical electrical connections, enabling high-speed data transmission in the Z-direction and achieving high interconnection performance through spatial dimensionality change
Solution Approach 2:
The patent implements nested structure where interconnect chips are bonded between device chips, and packaging layers are embedded within the stack. The via interconnection structure is nested within the packaging layers, creating a compact multi-layer integrated architecture that maximizes interconnection density while maintaining small volume
2Productivity
If via interconnection structure and multiple packaging layers are added to increase interconnection density, then communication speed between chips is improved, but device complexity increases
Solution Approach 1:
The packaging layers serve multiple functions simultaneously: they provide mechanical support for the chip stack, enable electrical insulation between conductive elements, facilitate heat dissipation pathways, and serve as structural substrates for bonding interconnect chips. This multi-functionality reduces the need for separate dedicated components, thereby managing complexity while achieving high interconnection density
Solution Approach 2:
The patent merges the interconnection function with the packaging structure by integrating via interconnection structures directly within the packaging layers. The interconnect chip bonding interfaces are combined with the packaging layer structure, eliminating the need for separate interconnection and packaging processes, thus reducing overall device complexity
3Manufacturing precision
If multiple carriers are used in the packaging process, then manufacturing precision can be maintained, but packaging cost increases
Solution Approach 1:
The method performs preliminary alignment and bonding of device chips to the carrier before forming the first packaging layer. The carrier serves as a temporary precision platform that maintains chip positions during subsequent processing steps. This preliminary action enables high manufacturing precision to be achieved while using a single carrier throughout the process, reducing overall manufacturing cost
Data Source
AI summary
A packaging structure and a packaging method are provided. The packaging method includes: providing a carrier; providing a plurality of device chips, a device chip including a first side and a second side, and a first interconnection structure being formed on the first side; attaching the plurality of device chips to the carrier; forming a first packaging layer covering a side wall of the device chip and filling between device chips on the carrier; providing an interconnect chip, a second interconnection structure being formed on the interconnect chip, and the second interconnection structure exposing a surface of the interconnect chip; bonding the interconnect chip to the device chip and the first packaging layer, the second interconnection structure of the interconnect chip facing and contacting the first interconnection structure of the device chip; and forming a second packaging layer covering the interconnect chip on the first packaging layer.